# US 2010/0169704 A1 · Ethernet System and Related Clock Synchronization Method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0169704 A1 - Document ID: US20100169704A1 - Status: Published application - Kind: A1 - Application number: 12/629,897 - Filed: 2009-12-03 - Published: 2010-07-01 - Earliest claimed: 2008-12-03 - Assignees: Realtek Semiconductor Corp. - Inventors: Ting-Fa Yu; Liang-Wei Huang; Rong-Jen Chang; Ming-Je Li - Web page: https://patentgrep.com/patent/US20100169704A1 ## CPC - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock. ## Claims ### Claim 1 A master device for an Ethernet system, the master device comprising: a receiver for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode, the transmission data comprising phase information of a recovery clock of the slave device; a buffer, coupled to the receiver, for accumulating the phase adjustment data and outputting a phase adjustment value; a phase lock loop unit, coupled to the buffer, for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock; and a transmitter for transmitting initialization data to the slave device according to the output clock. ### Claim 2 (depends on 1) The master device of claim 1, wherein the switch mode is entering a wake-up mode from a quiet mode. ### Claim 3 (depends on 1) The master device of claim 1, the Ethernet system is a Gigabit Ethernet system operated using an asymmetric mechanism. ### Claim 4 (depends on 1) The master device of claim 1, wherein the receiver comprises: a reception terminal for receiving the transmission data sent by the slave device; a data estimation unit coupled to the reception terminal for generating error information according to the transmission data sent by the slave device; and a digital recovery circuit for generating the phase adjustment value according to the error information. ### Claim 5 A synchronization method for a master device in an Ethernet system, the synchronization method comprising: generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode, the transmission data comprising phase information of a recovery clock of the slave device; accumulating the phase adjustment data and outputting a phase adjustment value; adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock; and transmitting initialization data to the slave device according to the output clock. ### Claim 6 (depends on 5) The synchronization method of claim 5, wherein the switch mode is entering a wake-up mode from a quiet mode. ### Claim 7 (depends on 5) The synchronization method of claim 5, wherein the Ethernet system is a Gigabit Ethernet system operated using an asymmetric mechanism. ### Claim 8 (depends on 5) The synchronization method of claim 5, wherein generating the phase adjustment data according to the transmission data sent by the slave device comprises: receiving the transmission data sent by the slave device; generating error information according to the transmission data sent by the slave device; and generating the phase adjustment value according to the error information. ### Claim 9 A master device for an Ethernet system, for synchronizing with a slave device, the master device comprising: a receiver for receiving transmission data from a slave device, the transmission data comprising phase information of a recovery clock; a transmitter operating according to a first clock; a detection unit coupled to the receiver and the transmitter for detecting a phase difference between clocks of the master device and the slave device according to the first clock and the recovery clock; and a synchronization unit, coupled to the detection unit, for comparing the phase difference with a tolerance value and controlling the master device to execute a process for synchronization with the slave device when the phase difference exceeds the tolerance value. ### Claim 10 (depends on 9) The master device of claim 9, wherein the master device is operated in a quiet mode. ### Claim 11 (depends on 9) The master device of claim 9, wherein the Ethernet system is a Gigabit Ethernet system operated using an asymmetric mechanism. ### Claim 12 (depends on 9) The master device of claim 9, wherein the process for synchronization with the slave device controls the master device to enter a wake-up mode from the quiet mode, and controls the transmitter to send an idle sequence to the slave device. ### Claim 13 A method for performing synchronization between a master device and a slave device in an Ethernet system, the method comprising: receiving transmission data from the slave device, the transmission data comprising phase information of a recovery clock; detecting a phase difference between clocks of the master device and the slave device according to the first clock and the recovery clock; and comparing the phase difference with a tolerance value, and controlling the master device to execute a process for synchronization with the slave device when the phase difference exceeds the tolerance value. ### Claim 14 (depends on 13) The method of claim 13, wherein the master device is operated in a quiet mode. ### Claim 15 (depends on 13) The method of claim 13, wherein the Ethernet system is a Gigabit Ethernet system operated using an asymmetric mechanism. ### Claim 16 (depends on 13) The method of claim 13, wherein the process for synchronization with the slave device controls the master device to enter a wake-up mode from the quiet mode, and controls the transmitter to send an idle sequence to the slave device. ### Claim 17 A slave device for reducing synchronization power consumption for an Ethernet system comprising a master device, the slave device comprising: a receiver for receiving an idle sequence from the master device; a transmitter for transmitting data to the master device according to an output clock; an operation unit, coupled to the receiver, for generating a phase difference according to the idle sequence; and a clock adjustment unit, coupled to the operation unit, for adjusting the output clock according to the phase difference. ### Claim 18 (depends on 17) The slave device of claim 17, wherein the Ethernet system is a Gigabit Ethernet system operated using an asymmetric mechanism. ### Claim 19 (depends on 17) The slave device of claim 17, wherein the idle sequence comprises clock information corresponding to the master device. ### Claim 20 (depends on 19) The slave device of claim 19, wherein the clock adjustment unit adjusts the output clock according to the clock information when the phase difference is greater than a threshold value. ### Claim 21 A method of reducing synchronization power consumption for a slave device in an Ethernet system comprising a master device, the method comprising: receiving an idle sequence from the master device; generating a phase difference according to the idle sequence; adjusting an output clock according to the phase difference; and transmitting data to the master device according to the output clock. ### Claim 22 (depends on 21) The method of claim 21, wherein the Ethernet system is a Gigabit Ethernet system operated using an asymmetric mechanism. ### Claim 23 (depends on 21) The method of claim 21, wherein the idle sequence comprises clock information corresponding to the master device. ### Claim 24 (depends on 23) The method of claim 23, wherein the clock adjustment unit adjusts the output clock according to the clock information when the phase difference is greater than a threshold value.