# US 2010/0169700 A1 · Adaptive clock enable for memory control

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- Number: US 2010/0169700 A1
- Document ID: US20100169700A1
- Status: Published application
- Kind: A1
- Application number: 12/317,869
- Filed: 2008-12-29
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Inventors: Philip Abraham; Steve Kulick; Mahadev Nemani
- Web page: https://patentgrep.com/patent/US20100169700A1

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3225: of memory devices
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In some embodiments a memory rank idle counter enables de-assertion of a clock enable signal of a rank of a memory for idle systems. Clock enable signal assertion is maintained when there is a lot of traffic to the memory rank. A memory rank idle time prediction counter transfers a value to the memory rank idle counter when the memory rank is idle. Other embodiments are described and claimed.

## Claims

### Claim 1

An apparatus comprising:
a memory rank idle counter to enable de-assertion of a clock enable signal of a rank of a memory for idle systems and to keep the clock enable signal asserted when there is a lot of traffic to the memory rank; and
a memory rank idle time prediction counter to transfer a value to the memory rank idle counter when the memory rank is idle.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising an adaptive window counter, the memory rank idle counter to update only when the adaptive window counter expires.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the memory rank idle prediction counter to decrement every time no new requests have arrived at the memory rank.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the apparatus is included in a memory controller.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the memory rank idle counter is to adjust the assertion and/or the de-assertion of the clock enable signal of the memory rank by dynamically adapting a delay between rank idle and power down using past traffic to the memory rank.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising for a second rank of the memory:
a memory rank idle counter to enable de-assertion of a clock enable signal of the second rank of the memory for idle systems and to keep the clock enable signal of the second rank of the memory asserted when there is a lot of traffic to the second memory rank; and
a memory rank idle time prediction counter to transfer a value to the memory rank idle counter of the second rank of the memory when the second memory rank is idle.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising for each rank of the memory:
a memory rank idle counter to enable de-assertion of a clock enable signal of that rank of the memory for idle systems and to keep the clock enable signal of the second rank of the memory asserted when there is a lot of traffic to that memory rank; and
a memory rank idle time prediction counter to transfer a value to the memory rank idle counter of that rank of the memory when that memory rank is idle.

### Claim 8

A system comprising:
a memory including a clock enable signal of a rank of the memory; and
a memory controller including:
a memory rank idle counter to enable de-assertion of the clock enable signal of a rank of a memory for idle systems and to keep the clock enable signal asserted when there is a lot of traffic to the memory rank; and
a memory rank idle time prediction counter to transfer a value to the memory rank idle counter when the memory rank is idle.

### Claim 9 (depends on 8)

The system of claim 8, the memory controller further including an adaptive window counter, the memory rank idle counter to update only when the adaptive window counter expires.

### Claim 10 (depends on 8)

The system of claim 8, wherein the memory rank idle prediction counter to decrement every time no new requests have arrived at the memory rank.

### Claim 11 (depends on 8)

The system of claim 8, wherein the memory rank idle counter is to adjust the assertion and/or the de-assertion of the clock enable signal of the memory rank by dynamically adapting a delay between rank idle and power down using past traffic to the memory rank.

### Claim 12 (depends on 8)

The system of claim 8, the memory controller further including for a second rank of the memory:
a memory rank idle counter to enable de-assertion of a clock enable signal of the second rank of the memory for idle systems and to keep the clock enable signal of the second rank of the memory asserted when there is a lot of traffic to the second memory rank; and
a memory rank idle time prediction counter to transfer a value to the memory rank idle counter of the second rank of the memory when the second memory rank is idle.

### Claim 13 (depends on 8)

The system of claim 8, the memory controller further including for each rank of the memory:
a memory rank idle counter to enable de-assertion of a clock enable signal of that rank of the memory for idle systems and to keep the clock enable signal of that rank of the memory asserted when there is a lot of traffic to that memory rank; and
a memory rank idle time prediction counter to transfer a value to the memory rank idle counter of that rank of the memory when that memory rank is idle.

### Claim 14

A method comprising:
enabling de-assertion of a clock enable signal of a rank of a memory for idle systems; and
keeping the clock enable signal asserted when there is a lot of traffic to the memory rank.

### Claim 15 (depends on 14)

The method of claim 14, further comprising adjusting the assertion and/or the de-assertion of the clock enable signal of the memory rank by dynamically adapting a delay between rank idle and power down using past traffic to the memory rank.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
enabling de-assertion of a clock enable signal of a second rank of the memory for idle systems; and
keeping the clock enable signal of the second rank of the memory asserted when there is a lot of traffic to the second memory rank.

### Claim 17 (depends on 14)

The method of claim 14, further comprising for each rank of the memory:
enabling de-assertion of a clock enable signal of that rank of the memory for idle systems; and
keeping the clock enable signal of that rank of the memory asserted when there is a lot of traffic to that memory rank.