# US 2010/0169699 A1 · Memory device, host device, and sampling clock adjusting method

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- Number: US 2010/0169699 A1
- Document ID: US20100169699A1
- Status: Published application
- Kind: A1
- Application number: 12/558,987
- Filed: 2009-09-14
- Published: 2010-07-01
- Earliest claimed: 2008-12-26
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Akihisa FUJIMOTO
- Web page: https://patentgrep.com/patent/US20100169699A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 13/4291: {using a clocked protocol}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

## Claims

### Claim 1

A memory device comprising:
a nonvolatile semiconductor memory unit;
a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal when the memory controller controls sending and receiving of the command signal and the response signal through a command line to and from a host device to which the memory device is connected, sending and receiving of the data signal and the status signal through a data line to and from the host device, and receiving of a clock signal through a clock line from the host device; and
a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to the host device, the tuning pattern signal being used by the host device to adjust a phase of the clock signal for use as a sampling clock signal.

### Claim 2 (depends on 1)

The memory device according to claim 1, wherein:
the memory-side pattern signal storage unit stores first and second tuning pattern signals; and
the memory controller sends to the host device the first tuning pattern signal through the command line and the second tuning pattern signal through the data line, and a time period during which the first tuning pattern signal is sent and a time period during which the second tuning pattern signal is sent overlap each other.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein the first and second tuning pattern signals enable detection of interference between the command line and the data line.

### Claim 4 (depends on 3)

The memory device according to claim 3, wherein the memory-side pattern signal storage unit stores a plurality of tuning pattern signal sets, each including the first and second tuning pattern signals, and one of the plurality of tuning pattern signal sets is selected and sent to the host device in response to a command from the host device.

### Claim 5 (depends on 4)

The memory device according to claim 4, further comprising a synchronization header signal output unit configured to output a synchronization header signal to be added to the data signal, the response signal, and the status signal and sent to the host device in order for the host device to fine-adjust a phase of the sampling clock signal.

### Claim 6 (depends on 5)

The memory device according to claim 5, wherein the synchronization header signal is a 4-bit signal including data “0101”.

### Claim 7 (depends on 6)

The memory device according to claim 6, wherein the memory controller sends the tuning pattern signals as the response signal and the data signal in response to receipt of a tuning command as the command signal from the host device.

### Claim 8 (depends on 7)

The memory device according to claim 7, wherein the nonvolatile semiconductor memory unit is a NAND flash memory unit.

### Claim 9 (depends on 8)

The memory device according to claim 8, which is a memory card.

### Claim 10

A host device comprising:
a clock configured to generate a clock signal;
a host controller configured to perform control for sending a command signal and a data signal in synchronization with the clock signal to a memory device having a nonvolatile semiconductor memory unit and being connected to the host device and for receiving from the memory device a response signal, a data signal, and a status signal in synchronization with a sampling clock signal, the sampling clock signal being the clock signal whose phase is adjusted, when the host controller controls sending and receiving of the command signal and the response signal through a command line, sending and receiving of the data signal through a data line, receiving of the status signal through a data line, and sending of the clock signal through a clock line;
a sampling clock adjustment unit configured to adjust a phase of the sampling clock signal; and
a host-side pattern signal storage unit configured to pre-store a tuning pattern signal having the same pattern as a tuning pattern signal sent from the memory device for adjusting the phase of the sampling clock signal.

### Claim 11 (depends on 10)

The host device according to claim 10, wherein the host-side pattern signal storage unit stores first and second tuning pattern signals, and the host device further comprises:
an interference detecting unit configured to compare the first tuning pattern signal received from the memory device through the command line and the second tuning pattern signal received from the memory device through the data line in a time period overlapping a time period during which the first tuning pattern signal is received with the first and second tuning pattern signals pre-stored in the host-side pattern signal storage unit to detect whether there is a difference; and
a sampling clock adjustment unit configured to adjust the phase of the sampling clock to prevent the difference.

### Claim 12 (depends on 11)

The host device according to claim 11, wherein the host-side pattern signal storage unit stores a plurality of tuning pattern signal sets, each including the first and second tuning pattern signals, and which of the plurality of tuning pattern signal sets is to be used is sent to the memory device with the command signal.

### Claim 13 (depends on 12)

The host device according to claim 12, further comprising a sampling clock fine-adjustment unit configured to fine-adjust the phase of the sampling clock signal on the basis of a synchronization header signal added to the data signal or the command signal received from the memory device.

### Claim 14 (depends on 13)

The host device according to claim 13, wherein the nonvolatile semiconductor memory unit of the memory device is a NAND flash memory unit.

### Claim 15 (depends on 14)

The host device according to claim 14, wherein the memory device is a memory card.

### Claim 16

A sampling clock adjusting method for a host device connected to a memory device including a nonvolatile semiconductor memory unit and configured to send and receive a command signal and a response signal to and from the memory device through a command line, send and receive a data signal to and from the memory device through a data line, receive a status signal through a data line from the memory device, and send a clock signal to the memory device through a clock line, the method comprising:
setting a sampling clock signal determining a sampling point at which the host device receives the data signal from the memory device in order to set an initial value of the phase of the sampling clock signal;
sending from the host device to the memory device a tuning command for adjusting the phase of the sampling clock signal from the clock signal through the command line;
receiving, by the host device, a first tuning pattern signal as a response signal sent through the command line from the memory device in response to the tuning command; and
adjusting, by the host device, the sampling clock signal on the basis of the received first tuning pattern signal.

### Claim 17 (depends on 16)

The sampling clock adjusting method according to claim 16, wherein:
in the receiving the tuning pattern signal, a second tuning pattern signal for sending and receiving the data signal is received by the host device from the memory device through the data line in a time period overlapping a time period during which the first tuning pattern signal is received;
the method further comprises comparing the first and second tuning pattern signals received from the memory device with the first and second tuning pattern signals stored in a host-side pattern signal storage unit to detect interference between the command line and the data line; and
in the adjusting the sampling clock, adjusting the sampling clock so that the comparison performed in the detecting an interference results in a match.

### Claim 18 (depends on 17)

The sampling clock adjusting method according to claim 17, further comprising:
receiving at the host device from the memory device any of the data signal to which a synchronization header signal is added through the data line, the status signal to which the synchronization header signal is added through the data line, or the response signal to which the synchronization header signal is added through the command line; and
fine-adjusting sampling points at which the data signal, the status signal and the response signal are received, on the basis of the synchronization header signal.

### Claim 19 (depends on 18)

The sampling clock adjusting method according to claim 18, wherein the nonvolatile semiconductor memory unit of the memory device is a NAND flash memory unit.

### Claim 20 (depends on 19)

The sampling clock adjusting method according to claim 19, wherein the memory device is a memory card.