# US 2010/0169696 A1 · Processor system employing a signal acquisition managing device and signal acquisition managing device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2010/0169696 A1
- Document ID: US20100169696A1
- Status: Published application
- Kind: A1
- Application number: 12/347,388
- Filed: 2008-12-31
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: STMicroelectronics S.r.l.; Freescale Semiconducteurs France SAS
- Inventors: Giuseppe D'Angelo; Antonio Anastasio; Leos Chalupa
- Web page: https://patentgrep.com/patent/US20100169696A1

## CPC

- B60W 50/0098: {Details of control systems ensuring comfort, safety or stability not otherwise provided for}
- B60W: CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT

## Abstract

A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm.

## Claims

### Claim 1

A processor system for use with an external apparatus, the system comprising:
a processor core configured to control the external apparatus in accordance with a control algorithm;
a signal acquisition managing device configured to receive state signals provided by the apparatus and to generate corresponding synchronized command signals which are synchronized relative to a control period; and
a peripheral module structured to receive the synchronized command signals, to perform actions corresponding to command signals, and to generate output signals to be processed by the processor core in accordance with the control algorithm.

### Claim 2 (depends on 1)

The system of claim 1, wherein the peripheral module includes:
at least one output analog-to-digital converter configured to receive first synchronized command signals and generate digital state data from the received state signals.

### Claim 3 (depends on 2)

The system of claim 2, wherein the peripheral module further includes:
at least one output timer configured to receive second synchronized command signals and to generate measuring signals from the received state signals.

### Claim 4 (depends on 1)

The system of claim 1, further comprising:
an input module connectable to the apparatus and structured to supply the state signals to the signal acquisition managing device.

### Claim 5 (depends on 4)

The system of claim 4, wherein said input module comprises at least one device belonging to the group comprising a Pulse Width Modulation duty cycle decoder, an analog-to-digital converter, a timer unit, a sensor, a position counter, a quadrature decoder, a resolver sensor, and a sine-cos sensor.

### Claim 6 (depends on 5)

The system of claims 5, wherein said processor core is configured to process the output signals provided by the peripheral module in accordance with a PWM technique.

### Claim 7 (depends on 6)

The system of claim 6, wherein said apparatus comprises from among the group consisting of at least one of: a direct current electrical motor, a single-phase electrical motor, a multi-phase electrical motor, air bag system, a DC/DC converter, a solenoid, a resolver sensor, and a sine-cosine sensor.

### Claim 8 (depends on 7)

The system of claim 7, wherein the input module is configured to receive first signals representing electrical currents or second signals representing actuator positions or third signals representing generated PWM signals or fourth signals representing the real PWM signals applied to the actuator or fifth digital signals representing an external synchronization event and providing a corresponding state signal.

### Claim 9 (depends on 4)

The system of claim 4, wherein the state signals provided by the input module comprises a control period signal indicated the control period used by the control algorithm.

### Claim 10 (depends on 1)

The system of claim 1, further comprising:
a memory configured for storing said output signals, said memory adapted to be readable by said processor core; and
a memory interface device configured to allow access of the signal acquisition managing device to the memory.

### Claim 11 (depends on 1)

The system of claim 1, wherein said signal acquisition managing device includes:
a plurality of input terminals structured to receive the state signals;
a trigger generation unit configured to build from the state signals a reference signal and generate event trigger signals, each representing a time in which an event has to be performed; and
a scheduler unit structured to associate each event trigger signal with a synchronized command signal to be supplied towards the peripheral module and representing the event to be performed.

### Claim 12 (depends on 11)

The system of claim 11, wherein the trigger generation unit comprises:
a selector device adapted to build the reference signal indicating a control cycle comprised between two occurrences of the reference signal;
a counter device structured to provide a counting value;
a comparator device adapted to compare said counting value to memorized delay values and generate the event trigger signals based on the comparing results.

### Claim 13 (depends on 11)

The system of claim 11, wherein the comparator device is structured to generate the event trigger signals within the control cycle, the event trigger signals delayed with respect to a first occurrence of the reference signal by said delay values.

### Claim 14 (depends on 13)

The system of claim 13, wherein the comparator device includes registers to store said delay values; the registers are structured to be re-loaded at a second occurrence of the reference signal.

### Claim 15 (depends on 11)

The system of claim 11, wherein
the selector device is adapted to select event signals among the state signals; and
the comparator is configured to generate the event trigger signals within the control cycle; each of said event trigger signals being delayed with respect to each event signal by corresponding delay amounts.

### Claim 16 (depends on 11)

The system of claim 11, wherein said scheduler unit includes:
at least one command generator providing said command signals;
a trigger handler which is configured to receives the event trigger signals and assign to each event trigger signal a corresponding output of the scheduler unit by driving said at least one command generator.

### Claim 17 (depends on 16)

The system of claim 16, wherein said command generator includes:
a first command generator structured to generate first command signals to be provided to an analog-to-digital converter; and
at least one second command generator configured to generate trigger signals to be provided to at least one timer.

### Claim 18

A signal acquisition managing device including:
a plurality of input terminals structured to receive state signals;
a trigger generation unit configured to build from the state signals a reference signal and generate event trigger signals, each representing a time in which an event has to be performed; and
a scheduler unit structured to associate each event trigger signal with a synchronized command signal to be supplied towards an external peripheral module and representing the event to be performed.

### Claim 19 (depends on 18)

The acquisition managing device of claim 18, wherein said acquisition managing device is a sequential logic circuit integrated in a semiconductor chip.

### Claim 20 (depends on 18)

The acquisition managing device of claim 18, wherein said scheduler unit includes:
a command list register structured to store data indicating command typology;
a command generator configured to generate the command signals based on said data stored into the command list register; and
a trigger handler which is configured to receives the event trigger signals and assign to each event trigger signal a corresponding output of the scheduler unit by driving said command generator.

### Claim 21

A circuit for controlling an external apparatus, the circuit comprising:
a signal acquisition managing device coupled to the external device to receive state signals from the external device, the signal acquisition managing device comprising:
a trigger generator unit that receives the state signals and generates a reference signal and plurality of event trigger signals that each represent an event performance time.

### Claim 22 (depends on 21)

The circuit of claim 21, wherein the signal acquisition managing device further comprises a scheduler unit coupled to the trigger generation unit to receive each of the plurality of event trigger signals and to associate each event trigger signal with a synchronized command signal.

### Claim 23 (depends on 22)

The circuit of claim 22, wherein the scheduler unit comprises at least one command generator providing the command signal and a trigger handler that is adapted to receive the event trigger signals and assign to each event trigger signal a corresponding output of the scheduler unit by driving the at least one command generator.

### Claim 24 (depends on 23)

The circuit of claim 23, wherein the command generator comprises a first command generator structured to generate first command signals to be provided to an analog-to-digital converter, and at least one second command generator configured to generate trigger signals to be provided at least one timer.

### Claim 25 (depends on 22)

The circuit of claim 22, wherein the trigger generation unit comprises a selector device adapted to build the reference signal that indicates a control cycle comprised between two occurrences of the reference signal; a counter device adapted to provide a counting value; and a comparator device adapted to compare the counting value to stored delay values and to generate the event trigger signals based on the results of the comparing of the counting value to the stored delay values.

### Claim 26 (depends on 25)

The circuit of claim 25, wherein the selector device is adapted to select event signals among the state signals and the comparator is configured to generate the event trigger signals within the control cycle, each of the event trigger signals being delayed with respect to each event signal by corresponding delay amounts.