# US 2010/0169693 A1 · State history storage for synchronizing redundant processors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0169693 A1 - Document ID: US20100169693A1 - Status: Published application - Kind: A1 - Application number: 12/347,961 - Filed: 2008-12-31 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: Intel Corporation - Inventors: Shubhendu S. Mukherjee; Arijit Biswas; Paul B. Racunas; Steven E. Raasch - Web page: https://patentgrep.com/patent/US20100169693A1 ## CPC - G06F 15/16: Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor G06F9/52; in regulating and control system G05B)} - G06F 11/1641: {where the comparison is not performed by the redundant processing components} - G06F 11/1683: {at instruction level} - G06F 11/1691: {using a quantum} - G06F 11/1407: {Checkpointing the instruction stream} - G06F 11/1658: {Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage. ## Claims ### Claim 1 An apparatus comprising: a first processor to execute a plurality of instructions; a first storage to store first processor state information for each instruction executed by the first processor from the plurality of instructions; a second processor to execute the plurality of instructions; a second storage to store second processor state information for each instruction executed by the second processor from the plurality of instructions; a controller to synchronize the first processor and the second processor based on at least one entry from the first storage and at least one entry from the second storage. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first storage is to store first processor state information for each instruction retired by the first processor from the plurality of instructions and the second storage is to store second processor state information for each instruction retired by the second processor from the plurality of instructions. ### Claim 3 (depends on 1) The apparatus of claim 1, further comprising a comparator to compare an entry in the first storage with an entry in the second storage. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the controller is to synchronize the first processor and the second processor based on the comparator indicating a match. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the plurality of instructions is a quantum of instructions in an instruction stream. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the controller is to synchronize the first processor and the second processor to begin execution from the same instruction boundary. ### Claim 7 (depends on 6) The apparatus of claim 6, further comprising an input replicator to replicate an input to be delivered to the first processor and the second processor. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the controller is to also to deliver a replicated input to the first processor and the second processor after synchronizing the first processor and the second processor. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the replicated input is an interrupt. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the controller is to synchronize the first processor and the second processor to begin execution from the same state. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the controller is to synchronize the first processor and the second processor to begin execution from the same state by restoring state of one of the first processor from the first storage and the second processor from the second storage. ### Claim 12 (depends on 1) The apparatus of claim 1, the first processor includes first state storage logic to compress and store the first processor state information and the second processor includes second state storage logic to compress and store the second processor state information. ### Claim 13 A method comprising: executing, by a first processor, a plurality of instructions; executing, by a second processor, the plurality of instructions; storing information representing state of the first processor at the retirement, by the first processor, of each instruction in the plurality of instructions; storing information representing state of the second processor at the retirement, by the second processor, of each instruction in the plurality of instructions; synchronizing the first processor and the second processor based on stored information representing past state of the first processor and stored information representing past state of the second processor. ### Claim 14 (depends on 13) The method of claim 13, further comprising comparing stored information representing past state of the first processor with stored information representing past state of the second processor. ### Claim 15 (depends on 14) The method of claim 14, wherein synchronizing is based on a match between stored information representing past state of the first processor and stored information representing past state of the second processor. ### Claim 16 (depends on 15) The method of claim 15, wherein synchronizing includes causing the first processor and the second processor to begin execution from the instruction boundary indicated by the match. ### Claim 17 (depends on 16) The method of claim 16, further comprising delivering an input to the first processor and the second processor after synchronizing and before beginning execution from the instruction boundary indicated by the match. ### Claim 18 (depends on 17) The method of claim 17, wherein synchronizing includes restoring state of one of the first processor from stored information representing past state of the first processor and the second processor from stored information representing past state of the second processor. ### Claim 19 A processor comprising: an execution core to execute a plurality of instructions; and storage to store state information for each instruction retired by the execution core, the storage accessible to a controller to synchronize the processor with a redundant processor. ### Claim 20 (depends on 19) The processor of claim 19, further comprising logic to store the state information.