# US 2010/0169690 A1 · System power management using memory throttle signal

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- Number: US 2010/0169690 A1
- Document ID: US20100169690A1
- Status: Published application
- Kind: A1
- Application number: 12/347,350
- Filed: 2008-12-31
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: Intel Corporation
- Inventors: Gopal Mundada; Xiuting (Kaleen) Man; Brian Griffith; Viktor D. Vogman; Richard Kaltenbach
- Web page: https://patentgrep.com/patent/US20100169690A1

## CPC

- G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
- G06F 1/3225: of memory devices
- G06F 11/3058: {Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

According to some embodiments, power information associated with a computing system may be monitored. Based on the monitored power information, it may be determined whether a hardware memory throttling signal will be asserted and/or that a processor power control signal will be asserted.

## Claims

### Claim 1

A method, comprising:
monitoring power information associated with a computing system; and
based on the monitored power information, determining whether a hardware memory throttling signal will be asserted.

### Claim 2 (depends on 1)

The method of claim 1, wherein the power information includes at least one of: (i) power supply information, (ii) an indication of whether one or more power supplies are installed, (ii) an indication of whether at least one power supply has failed, (iv) an indication of whether at least one power supply is exceeding a design/maximum continuous power limit, (v) an indication of whether one or more power supply input voltage/AC range has failed, or (vi) a system management bus signal.

### Claim 3 (depends on 1)

The method of claim 1, wherein the power information includes at least one of: (i) component power consumption information, (ii) an indication that a processor voltage regulator current trip point has been triggered, or (iii) an indication that a memory voltage regulator current trip point has been triggered.

### Claim 4 (depends on 1)

The method of claim 1, wherein the power information includes an indication of at least one of: (i) whether a system power utilization level exceeds a pre-determined limit, or (ii) whether multiple system power utilization levels exceed a pre-determined limit.

### Claim 5 (depends on 1)

The method of claim 1, wherein the computing system includes a plurality of memory components, and said determining comprising:
based on the monitored power information, determining whether a hardware memory throttling signal will be asserted for each of the plurality of memory components.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
based on the monitored power information, determining whether a hardware processor power control signal will be asserted.

### Claim 7 (depends on 6)

The method of claim 6, wherein the computing system includes a plurality of processors, and said determining comprising:
based on the monitored power information, determining whether a hardware processor power control signal will be asserted for each of the plurality of processors.

### Claim 8 (depends on 1)

The method of claim 1, wherein said determining is performed by a programmable logic device or discrete logic components on a board.

### Claim 9 (depends on 1)

The method of claim 1, wherein the hardware memory throttling signal causes a memory controller to force no-operation frames and reduce power consumption by a memory subsystem.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
asserting the hardware memory throttling signal.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
continuing to monitor power information associated with a computing system; and
based on the continued monitoring of the power information, determining that the hardware memory throttling signal will no longer be asserted.

### Claim 12

A system, comprising:
a memory throttling pin input associated with a memory element; and
a power manager coupled to the memory throttling pin and adapted to: (i) monitor power information associated with a computing system, and (ii) based on the monitored power information, determine whether a signal will be asserted on the memory throttling pin.

### Claim 13 (depends on 12)

The system of claim 12, wherein the power information includes (i) power supply information, (ii) component power consumption information, and (iii) an indication of whether a system power utilization level exceeds a pre-determined limit.

### Claim 14 (depends on 12)

The system of claim 12, further comprising:
a processor element with a processor power control pin input,
wherein the power manager is coupled to the processor power control pin and is further adapted to, based on the monitored power information, determine whether a signal will be asserted on the processor power control pin.

### Claim 15 (depends on 12)

The system of claim 12, wherein the power manager is associated with a programmable logic device or discrete logic components on a board.