# US 2010/0169599 A1 · Security management in system with secure memory secrets

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- Number: US 2010/0169599 A1
- Document ID: US20100169599A1
- Status: Published application
- Kind: A1
- Application number: 12/319,193
- Filed: 2008-12-31
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: Intel Corporation
- Inventors: Mahesh Natu; Shamanna Datta
- Web page: https://patentgrep.com/patent/US20100169599A1

## CPC

- G06F 12/1433: {for a module or a part of a module}
- G06F 21/71: to assure secure computing or processing of information
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In some embodiments a Trusted Platform Module (TPM) manages a first flag that identifies whether a secure environment has ever been established. A chipset manages a second flag that identifies that there might have been secrets in memory and a reset or power failure occurred. At least one processor and/or the chipset lock, maintain a lock, and/or unlock a memory in response to the second flag. Other embodiments are described and claimed.

## Claims

### Claim 1

An apparatus comprising:
at least one processor;
a Trusted Platform Module to manage a first flag that identifies whether a secure environment has ever been established;
a chipset to manage a second flag that identifies that there might have been secrets in memory and a reset or power failure occurred;
wherein the at least one processor and/or the chipset is/are to lock, to maintain a lock and/or to unlock a memory in response to the second flag.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first flag is one bit and/or wherein the second flag is one bit and both flags are non-volatile.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the processor and/or the chipset is to prevent accesses to the memory while the second flag is set.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the at least one processor and/or the chipset is/are to clear secrets from the memory in response to the second flag being set.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the processor and/or the chipset is/are to clear the second flag when it determines that the first flag is FALSE.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the secrets in memory include one or more of encryption keys, passwords, and/or personal data.

### Claim 7 (depends on 1)

The apparatus of claim 1, the chipset to manage a third non-volatile flag indicating that secrets have been placed in memory.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the third flag is a SECRETS flag.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the third flag is one bit.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first flag is an ESTABLISHED flag.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the second flag is a WAKE-ERROR.STS flag.

### Claim 12

A method comprising:
managing a first flag that identifies whether a secure environment has ever been established;
managing a second flag that identifies that there might have been secrets in memory and a reset or power failure occurred; and
locking, maintaining a lock, and/or unlocking a memory in response to the second flag.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first flag is one bit and/or wherein the second flag is one bit.

### Claim 14 (depends on 12)

The method of claim 12, further comprising preventing accesses to the memory while the second flag is set.

### Claim 15 (depends on 12)

The method of claim 12, further comprising clearing secrets from the memory in response to the second flag being set.

### Claim 16 (depends on 12)

The method of claim 12, further comprising clearing the second flag in response to the first flag being FALSE.

### Claim 17 (depends on 12)

The method of claim 12, wherein the secrets in memory include one or more of encryption keys, passwords, and/or personal data.

### Claim 18 (depends on 12)

The method of claim 12, further comprising managing a third flag indicating that secrets have been placed in memory.

### Claim 19 (depends on 18)

The method of claim 18, wherein the third flag is a SECRETS flag.

### Claim 20 (depends on 18)

The method of claim 18, wherein the third flag is one bit.

### Claim 21 (depends on 12)

The method of claim 12, wherein the first flag is an ESTABLISHED flag.

### Claim 22 (depends on 12)

The method of claim 12, wherein the second flag is a WAKE-ERROR.STS flag.

### Claim 23 (depends on 12)

The method of claim 12, further comprising managing various system fabrics connecting the processor and the chipset such that access to these flags return a predetermined value when fabrics are uninitialized or incorrectly initialized.