# US 2010/0169583 A1 · Multi-port memory device with serial input/output interface

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- Number: US 2010/0169583 A1
- Document ID: US20100169583A1
- Status: Published application
- Kind: A1
- Application number: 12/717,011
- Filed: 2010-03-03
- Published: 2010-07-01
- Earliest claimed: 2006-06-30
- Assignees: Hynix Semiconductor Inc.
- Inventors: Jin-Il Chung; Jae-II Kim; Chang-Ho Do; Hwang Hur
- Web page: https://patentgrep.com/patent/US20100169583A1

## CPC

- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 29/32: Serial access; Scan testing
- G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.

## Claims

### Claim 1

A multi-port memory device, comprising:
a plurality of ports (PORT0-PORT3); a first global data bus coupled to said ports;
a second global data bus coupled to said ports;
an I/O controller (91-94) corresponding to each of said plurality of ports, said I/O controller configured to transmit a test signal (P0_RXD) from its corresponding port (PORT0-PORT3) to the second global data bus (GIO_IN) when the multi-port memory device performs a DRAM core test operation;
a test I/O controller (95) which transmits a test I/O signal to the second global data bus (GIO_IN) in response to an internal write command, and transmits data input from the first global data bus (GIO_OUT) in response to an internal read command.

### Claim 2 (depends on 1)

The multi-port memory device as recited in claim 1, further comprising a mode register set for generating a test enable signal in response to a mode register enable signal and outputting a mode selection signal which determines a data transmission mode of said test I/O signal.

### Claim 3 (depends on 2)

The multi-port memory device as recited in claim 2, further comprising a clock generator for receiving an external clock and generating an internal clock based on the external clock in response to the mode selection signal.

### Claim 4 (depends on 2)

The multi-port memory device as recited in claim 2, further comprising a plurality of banks, each coupled to a corresponding one of said plurality of ports, wherein the mode register enable signal is active during a test operation mode for testing a core area of said banks.

### Claim 5 (depends on 1)

The multi-port memory device defined by claim 1, wherein the test signal (P0_RXD) is input to the ports (PORT0-PORT3) through I/O pads (RXi+, RXi−, TXi+, and TXi−) and a dummy pad (S1).

### Claim 6 (depends on 1)

The multi-port memory device defined by claim 1, wherein the I/O controller (91-94) includes an input driver for receiving the test signal (P0_RXD) and an output driver for outputting the test signal (P0_RXD) to the second global data bus (GIO_IN).

### Claim 7 (depends on 1)

The multi-port memory device defined by claim 1, wherein the test I/O signal is input/output through test pads (DQ0-DQ3) coupled to said test I/O controller (95).