# US 2010/0169581 A1 · Extending cache coherency protocols to support locally buffered data

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- Number: US 2010/0169581 A1
- Document ID: US20100169581A1
- Status: Published application
- Kind: A1
- Application number: 12/346,543
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Intel Corporation
- Inventors: Gad Sheaffer; Shlomo Raikin; Vadim Bassin; Raanan Sade; Ehud Cohen; Oleg Margulis
- Web page: https://patentgrep.com/patent/US20100169581A1

## CPC

- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/467: {Transactional memory (G06F9/528 takes precedence)}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/084: with a shared cache
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.

## Claims

### Claim 1

An apparatus comprising:
execution resources to execute a transactional store operation within a transaction referencing an address associated with a data item; and
a memory coupled to the execution resources to hold the data item in a buffered coherency state in response to the execution resources executing the transactional store operation.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory includes a cache memory coupled to the execution resources to hold the data item in a buffered coherency state, and wherein the cache memory comprises a cache line, which is to hold at least a portion of the data item, to be associated with the buffered coherency state.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein a cache line of the cache memory, which is to hold at least a portion of the data item, to be associated with the buffered coherency state comprises a state entry associated with the cache line holding a buffered state value to indicate the cache line is held in the buffered coherency state.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein further comprising control logic associated with the cache memory.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein a hardware monitor associated with the cache line is also to indicate the cache line buffered in response to the execution resources executing the transactional store operation.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the control logic is to detect a conflict at the time of an external access request in response to the control logic receiving the external access request and the hardware monitor indicating the cache line is buffered.

### Claim 7 (depends on 4)

The apparatus of claim 4, wherein a hardware read monitor associated with the cache line is also to indicate the cache line is read-monitored in response to the execution resources executing a local transactional read operation within the transaction.

### Claim 8 (depends on 4)

The apparatus of claim 4, wherein the control logic is to provide a miss-response responsive to the control logic receiving an external access request referencing the cache line and the cache line being associated with the buffered coherency state.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the control logic is to provide a hit-response responsive to the control logic receiving a local access request referencing the cache line and the cache line being associated with the buffered coherency state.

### Claim 10 (depends on 4)

The apparatus of claim 4, wherein the control logic is to transition the cache line from being associated with the buffered coherency state to a modified coherency state responsive to the transaction being committed.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the control logic is to transition the cache line from being associated with the buffered coherency state to a modified coherency state comprises the control logic to directly transition the cache line from being associated with the buffered coherency state to being associated with the modified coherency state.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the control logic is to transition the cache line from being associated with the buffered coherency state to a modified coherency state comprises the control logic to transition the cache line from being associated with the buffered coherency state to an intermediate buffered-modified coherency state and then clearing the buffered state to leave the cache line associated with the modified coherency state.

### Claim 13 (depends on 4)

The apparatus of claim 4, wherein the control logic is capable of accessing the buffered coherency state to be associated with the cache line responsive to a user-level instruction, and wherein the user-level instruction is selected from a group consisting of a set coherency state instruction, a clear coherency state instruction, and a test coherency state instruction.

### Claim 14

A processor comprising:
a cache memory to hold at least a portion of a data item in a cache line to be held in a buffered coherency state in response to performing a store operation, which is to reference the data item and is to be selected for buffering; and
control logic associated with the cache memory to provide a miss response in response to receiving an external access request associated with the cache line when the cache line is held in the buffered coherency state.

### Claim 15 (depends on 14)

The processor of claim 14, wherein the control logic is further to transition the cache line from being held in the buffered coherency state to an invalid coherency state in response to receiving the external access request associated with the cache line when the cache line is held in the buffered coherency state.

### Claim 16 (depends on 14)

The processor of claim 14, further comprising a first processing element to be associated with the store operation and a second processing element not associated with the store operation, wherein the external access request associated with the cache line includes an access request to access the data item associated with the second processing element.

### Claim 17 (depends on 14)

The processor of claim 14, further comprising decoder logic, wherein the store operation to be selected for buffering comprises the decoder logic to recognize the store operation as including a transactional store operation to be selected for buffering.

### Claim 18 (depends on 14)

The processor of claim 14, further comprising a user-accessible control register to hold a selective value to indicate a selective mode of buffering and a non-selective value to indicate a non-selective mode of buffering.

### Claim 19 (depends on 18)

The processor of claim 18, wherein the store operation to be selected for buffering comprises the user-accessible control register holding the selective value and a criteria associated with the store operation matching a selection criteria or the user-accessible control register holding the non-selective value.

### Claim 20 (depends on 14)

The processor of claim 14, further comprising a coherency state entry associated with the cache line, wherein the cache line to be held in the buffered coherency state includes the state entry holding a buffered coherency value.

### Claim 21

An apparatus comprising:
a cache memory to hold at least a portion of a data item in a cache line to be associated with a buffered coherency state in response to the data item being transactionally accessed within a transaction; and
control logic associated with the cache memory to transition the cache line from being associated with the buffered coherency state to a modified coherency state in response to the transaction being committed.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein a cache line to be associated with a buffered coherency state comprises a coherency entry associated with the cache line to hold a buffered coherency value.

### Claim 23 (depends on 22)

The apparatus of claim 22, wherein control logic to transition the cache line from being associated with the buffered coherency state to a modified coherency state comprises updating the coherency entry from holding the buffered coherency value to hold a modified coherency value.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein updating the coherency entry from holding the buffered coherency value to hold a modified coherency value comprises updating the coherency entry from holding the buffered coherency value to hold a buffered-modified intermediate coherency value and then clearing the buffered coherency value from the buffered-modified intermediate coherency value to form the modified coherency value.

### Claim 25 (depends on 24)

The apparatus of claim 24, wherein the coherency entry includes a bit vector, and wherein updating the coherency entry from holding the buffered coherency value to hold a buffered-modified intermediate coherency value and then clearing the buffered coherency value from the buffered-modified intermediate coherency value to leave the modified coherency value comprises setting a modified bit of the coherency entry to update the coherency entry from holding the buffered coherency value to hold the buffered-modified intermediate coherency value and then clearing a buffered bit of the coherency entry to leave the modified bit set for the modified coherency value.

### Claim 26 (depends on 21)

The apparatus of claim 21, wherein the transaction being committed is in response to execution of a user-level commit transaction instruction.

### Claim 27 (depends on 21)

The apparatus of claim 21, wherein the transaction being committed is in response to reaching the end of the transaction while not detecting any transaction related conflicts.

### Claim 28

A system comprising:
a processor including a memory comprising a line to hold at least a portion of a data item in a buffered state in response to the data item being transactionally written, and control logic coupled to the memory to provide a hit response responsive to a local access request to the line in the buffered state and to provide a miss responsive to a non-local access request to the line in the buffered state; and
an input/output (I/O) device coupled to the processor.

### Claim 29 (depends on 28)

The system of claim 28, wherein the control logic is further to transition the line from the buffered state to an invalid state responsive to the non-local access request to the line in the buffered state.

### Claim 30 (depends on 28)

The system of claim 28, wherein the control logic is further to transition the line from the buffered state to a modified state responsive to perform a commit operation for the line.

### Claim 31 (depends on 28)

The system of claim 28, wherein the processor further comprises a hardware write monitor to be set to indicate the line is write monitored in response to the data item being transactionally written and a hardware read monitor to be set to indicate the line is read monitored in response to the data item being transactionally read.

### Claim 32

A method comprising:
encountering a transactional store referencing an address associated with a data item;
performing a buffered store of the data item to associate the data item with a buffered state in response to encountering the transactional store; and
in response to the data item being associated with the buffered state, providing a hit response to a local access to the data item and providing a miss response to an external access to the data item.

### Claim 33 (depends on 32)

The method of claim 32, wherein the transactional store referencing the address includes an operation code (opcode) recognizable by decoder logic of a processor to indicate the transactional store is to be performed as a buffered store.

### Claim 34 (depends on 32)

The method of claim 32, wherein performing a buffered store of the data item to associate the data item with a buffered state comprises:
performing a buffered store of at least a portion of the data item to a cache line in a cache memory associated with the address associated with the data item; and
updating a coherency state entry corresponding to the cache line to a buffered state value to associate at least the portion of the data item held in the cache line with the buffered state.

### Claim 35 (depends on 34)

The method of claim 34, further comprising updating a write monitor associated with the cache line to a monitored state to indicate the cache line is write monitored in response to performing the buffered store of at least the portion of the data item to the cache line.

### Claim 36 (depends on 34)

The method of claim 34, further comprising updating the coherency state entry to an invalid state value to associate at least the portion of the data item held in the cache line with an invalid state in response to the data item being associated with the buffered state and providing a miss response to the external access to the data item.

### Claim 37 (depends on 34)

The method of claim 34, further comprising updating the coherency state entry to a modified state value to associate at least the portion of the data item held in the cache line with a modified state in response to the data item being associated with the buffered state and performing a commit associated with the data item.

### Claim 38 (depends on 34)

The method of claim 34, wherein updating the coherency state entry to a modified state value to associate at least the portion of the data item held in the cache line with a modified state comprises updating the coherency state entry to a modified-buffered state value and then clearing the buffered state value from the modified-buffered state value to leave the modified state value.