# US 2010/0169550 A1 · Semiconductor memory device, data transfer device, and method of controlling semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0169550 A1 - Document ID: US20100169550A1 - Status: Published application - Kind: A1 - Application number: 12/547,851 - Filed: 2009-08-26 - Published: 2010-07-01 - Earliest claimed: 2008-12-27 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Shingo Akita; Hiroshi Shimizu - Web page: https://patentgrep.com/patent/US20100169550A1 ## CPC - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 2212/214: Solid state disk - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract To provide a semiconductor memory device including a first controller that controls a first data transfer in which data are transferred from the first memory to a second memory in predetermined transfer units; a second controller that controls a second data transfer in which data are transferred from the second memory to a host device; and a control unit that outputs to the first controller a read instruction in which an address in the second memory is specified for each of the predetermined transfer units and creates a descriptor in which the addresses in the second memory are specified in order of transfer. The first controller outputs an end notification at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification. ## Claims ### Claim 1 A semiconductor memory device comprising: a nonvolatile first memory; a second memory used as a cache for transferring data between the first memory and a host device; a first controller that controls a first data transfer in which data are transferred from the first memory to the second memory in predetermined transfer units; a second controller that controls a second data transfer in which data are transferred from the second memory to the host device; and a control unit that, upon receipt of a read request from the host device, outputs to the first controller a read instruction in which an address in the second memory being a transfer-destination address of the first data transfer is specified for each of the predetermined transfer units, and creates a descriptor in which the addresses in the second memory being transfer-source addresses of the second data transfer are specified in order of transfer, wherein the first controller outputs an end notification to the second controller at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the read instruction causes the first data transfer to be executed on data not cached in the second memory, among data that are requested to read from the host device. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein the descriptor includes, for each of the transfer-source addresses of the second data transfer, a flag that indicates whether transfer-target data by the second data transfer is data previously cached in the second memory or data that is to be transferred from the first memory by the first data transfer, and the second controller determines, based on the flag, whether the transfer-target data by the second data transfer is the data previously cached in the second memory or the data to be transferred from the first memory by the first data transfer, executes the second data transfer on the data cached in the second memory after obtaining the descriptor, and executes the second data transfer on the data to be transferred from the first memory by the first data transfer after obtaining the descriptor and after receiving the end notification received from the first controller. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the first memory is a NAND flash memory, and the predetermined transfer unit is equal to a page being a collective write unit or a collective read unit of the NAND flash memory. ### Claim 5 (depends on 2) The semiconductor memory device according to claim 2, wherein the descriptor has a field that defines a data size of the transfer-target data by the second data transfer, and the second controller determines that the first data transfer corresponding to the data size is completed according to the data size and a count of the end notifications. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein in the field that defines the data size, a data size corresponding to a plurality of the predetermined transfer units can be written. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein the first controller and the second controller are connected by a dedicated line through which the end notification can be transferred as a pulse signal. ### Claim 8 A data transfer device that transfers data by using a second memory as a cache for transferring data between a nonvolatile first memory and a host device, the data transfer device comprising: a first controller that controls a first data transfer in which data are transferred from the first memory to the second memory in predetermined transfer units; a second controller that controls a second data transfer in which data are transferred from the second memory to the host device; and a control unit that, upon receipt of a read request from the host device, outputs to the first controller a read instruction in which an address in the second memory being a transfer-destination address of the first data transfer is specified for each of the predetermined transfer units, and creates a descriptor in which the addresses in the second memory being transfer-source addresses of the second data transfer are specified in order of transfer, wherein the first controller outputs an end notification to the second controller at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification. ### Claim 9 (depends on 8) The data transfer device according to claim 8, wherein the read instruction causes the first data transfer to be executed on data not cached in the second memory, among data that are requested to read from the host device. ### Claim 10 (depends on 9) The data transfer device according to claim 9, wherein the descriptor includes, for each of the transfer-source addresses of the second data transfer, a flag that indicates whether transfer-target data by the second data transfer is data previously cached in the second memory or data that is to be transferred from the first memory by the first data transfer, and the second controller determines, based on the flag, whether the transfer-target data by the second data transfer is the data previously cached in the second memory or the data to be transferred from the first memory by the first data transfer, executes the second data transfer on the data cached in the second memory after obtaining the descriptor, and executes the second data transfer on the data to be transferred from the first memory by the first data transfer after obtaining the descriptor and after receiving the end notification received from the first controller. ### Claim 11 (depends on 8) The data transfer device according to claim 8, wherein the first memory is a NAND flash memory, and the predetermined transfer unit is equal to a page being a collective write unit or a collective read unit of the NAND flash memory. ### Claim 12 (depends on 9) The data transfer device according to claim 9, wherein the descriptor has a field that defines a data size of the transfer-target data by the second data transfer, and the second controller determines that the first data transfer corresponding to the data size is completed according to the data size and a count of the end notifications. ### Claim 13 (depends on 12) The data transfer device according to claim 12, wherein in the field that defines the data size, a data size corresponding to a plurality of the predetermined transfer units can be written. ### Claim 14 (depends on 8) The data transfer device according to claim 8, wherein the first controller and the second controller are connected by a dedicated line through which the end notification can be transferred as a pulse signal. ### Claim 15 A method of controlling a semiconductor memory device that includes: a nonvolatile first memory; a second memory used as a cache for transferring data between the first memory and a host device; a first controller that controls a first data transfer in which data are transferred from the first memory to the second memory in predetermined transfer units; and a second controller that controls a second data transfer in which data are transferred from the second memory to the host device, the method comprising: upon receipt of a read request from the host device, outputting to the first controller a read instruction in which an address in the second memory being a transfer-destination address of the first data transfer is specified for each of the predetermined transfer units and creating a descriptor in which the addresses in the second memory being transfer-source addresses of the second data transfer are specified in order of transfer; causing the first controller to output an end notification to the second controller at each end of the first data transfer; and causing the second controller to execute the second data transfer according to the specification in the descriptor after receiving the end notification. ### Claim 16 (depends on 15) The method of controlling a semiconductor memory device according to claim 15, wherein the read instruction causes the first data transfer to be executed on data not cached in the second memory, among data that are requested to read from the host device. ### Claim 17 (depends on 16) The method of controlling a semiconductor memory device according to claim 16, wherein the descriptor includes, for each of the transfer-source addresses of the second data transfer, a flag that indicates whether transfer-target data by the second data transfer is data previously cached in the second memory or data that is to be transferred from the first memory by the first data transfer, and the second controller is caused to determine, based on the flag, whether the transfer-target data by the second data transfer is the data previously cached in the second memory or the data to be transferred from the first memory by the first data transfer, to execute the second data transfer on the data cached in the second memory after obtaining the descriptor, and to execute the second data transfer on the data to be transferred from the first memory by the first data transfer after obtaining the descriptor and after receiving the end notification received from the first controller. ### Claim 18 (depends on 15) The method of controlling a semiconductor memory device according to claim 15, wherein the first memory is a NAND flash memory, and the predetermined transfer unit is equal to a page being a collective write unit or a collective read unit of the NAND flash memory. ### Claim 19 (depends on 16) The method of controlling a semiconductor memory device according to claim 16, wherein the descriptor has a field that defines a data size of the transfer-target data by the second data transfer, and the second controller is caused to determine that the first data transfer corresponding to the data size is completed according to the data size and a count of the end notifications. ### Claim 20 (depends on 15) The method of controlling a semiconductor memory device according to claim 15, wherein the first controller and the second controller are connected by a dedicated line through which the end notification can be transferred as a pulse signal.