# US 2010/0169528 A1 · Interrupt technicques

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- Number: US 2010/0169528 A1
- Document ID: US20100169528A1
- Status: Published application
- Kind: A1
- Application number: 12/319,033
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Intel Corporation
- Inventors: Amit Kumar; Steven King; Ram Huggahalli; Xia Zhu; Mazhar Memon; Frank Berry; Nitin Bhardwaj; Theodore Willke, II
- Web page: https://patentgrep.com/patent/US20100169528A1

## CPC

- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- H04L 49/90: Buffering arrangements
- H04L 49/9094: {Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space.

## Claims

### Claim 1

A method comprising:
receiving contents of a network protocol unit from one or more message segments at a queue associated with a message engine; and
indicating availability of contents of the queue to a core using an interrupt.

### Claim 2 (depends on 1)

The method of claim 1, wherein the indicating availability of contents of the queue from the message engine to a core using an interrupt comprises generating an inter-processor interrupt.

### Claim 3 (depends on 1)

The method of claim 1, wherein the indicating availability of contents of the queue from the message engine to a core using an interrupt comprises writing an MSI-X message in an MSI-X memory region.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
the core programming a rate at which the message engine can interrupt the core.

### Claim 5 (depends on 4)

The method of claim 4, wherein the core programming a rate comprises the core writing to a register in the coherent memory domain.

### Claim 6 (depends on 1)

The method of claim 1, wherein the network protocol unit is Ethernet compliant.

### Claim 7 (depends on 1)

The method of claim 1, wherein at least one of the message segments comprises:
a link layer;
a destination virtual message engine address;
a reassembly tag field;
a message segment offset field; and
a data portion.

### Claim 8 (depends on 7)

The method of claim 7, wherein the queue is based on the reassembly tag field and further comprising:
a buffer in the queue based on the reassembly tag field; and
a location in the buffer to store at least one of the message segments based in part on the message segment offset field.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
receiving an indication of a page fault when attempting to write contents of the one or more message segments to the queue; and
indicating the page fault to the core using a second interrupt.

### Claim 10 (depends on 9)

The method of claim 9, wherein the indicating availability of contents of the queue to the core using an interrupt comprises generating an inter-processor interrupt.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
receiving a second network protocol unit;
transmitting contents of the network protocol unit using one or more message segments to a second queue associated with a second message engine; and
indicating availability of contents of the second queue to a second core using a second interrupt.

### Claim 12

An apparatus comprising:
a queue to receive contents of a network protocol unit from one or more message segments; and
a core; and
a message engine to indicate availability of the contents of the queue to the core using an interrupt.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein to indicate availability of contents of the queue from the message engine to the core, the message engine is to generate an inter-processor interrupt.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein to indicate availability of contents of the queue from the message engine to the core, the message engine is to write an MSI-X message in an MSI-X memory region.

### Claim 15 (depends on 12)

The apparatus of claim 12, wherein the core programs a rate at which the message engine is permitted to interrupt the core.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the core programs a rate at which the message engine is permitted to interrupt the core by writing a register in the coherent memory domain.

### Claim 17 (depends on 12)

The apparatus of claim 12, wherein at least one of the message segments comprises:
a link layer;
a destination virtual message engine address;
a reassembly tag field;
a message segment offset field; and
a data portion.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the queue is based on the reassembly tag field and further comprising:
a buffer in the queue based on the reassembly tag field; and
a location in the buffer to store at least one of the message segments based in part on the message segment offset field.

### Claim 19 (depends on 12)

The apparatus of claim 12, further comprising:
a second queue, wherein:
in response to receiving an indication of a page fault when attempting to write contents of the one or more message segments to the second queue, the message engine is to indicate the page fault to the core using an interrupt.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein to indicate availability of contents of the second queue to the core, the message engine is to generate an inter-processor interrupt.

### Claim 21 (depends on 12)

The apparatus of claim 12, wherein the core is to regulate the rate at which the core receives interrupts.

### Claim 22

A system comprising:
a storage device;
at least one core;
a network interface to receive a network protocol unit; and
first and second message engines, wherein
the first message engine is to form at least one message from contents of the network protocol unit and to transmit the at least one message to the second message engine without sharing memory space and
the second message engine is to notify one of the at least one core of availability of the message using an interrupt.

### Claim 23 (depends on 22)

The system of claim 22, wherein to notify one of the at least one core of availability of the message using an interrupt, the second message engine is to generate an inter-processor interrupt.

### Claim 24 (depends on 22)

The system of claim 22, wherein at least one core is to program a rate at which the second message engine is to generate interrupts.

### Claim 25 (depends on 22)

The system of claim 22, wherein the message engine comprises:
a message mapper to determine a destination virtual message engine associated with the network protocol unit; and
logic to transmit content of the network protocol unit using at least one message to a queue associated with the destination virtual message engine.

### Claim 26 (depends on 22)

The system of claim 22, wherein the message engine is to form at least one segment from the at least one message.