# US 2010/0167669 A1 · Discrete filter, sampling mixer, and radio device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0167669 A1 - Document ID: US20100167669A1 - Status: Published application - Kind: A1 - Application number: 12/303,936 - Filed: 2007-06-08 - Published: 2010-07-01 - Earliest claimed: 2006-06-08 - Assignees: Panasonic Corporation - Inventors: Yoshifumi Hosokawa; Katsuaki Abe; Kentaro Miyano - Web page: https://patentgrep.com/patent/US20100167669A1 ## CPC - H03H 15/00: Transversal filters (electromechanical filters H03H9/46, H03H9/70) - G11C 27/024: {using a capacitive memory element (G11C27/04 takes precedence)} - H03D 7/1441: {using field-effect transistors (H03D7/145 takes precedence)} - H03D 7/1483: {comprising components for selecting a particular frequency component of the output} - H03D 7/166: {using two or more quadrature frequency translation stages} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) ## Abstract Provided is a discrete filter capable of adjusting the number of notches and the notch frequency and easily eliminating a particular frequency component. In a sampling mixer (100), a control signal generation unit (104) generates a plurality of control signals having the same frequency and different phases. A convolution capacity unit (110) integrates the discrete signals obtained by sampling reception signals by using convolution capacitors at a timing based on the control signals. The signals integrated by the convolution capacitors are successively emitted at the timing based on a control signal other than the control signals used for the integration timing. Cb (15) integrates the emitted discrete signals. Thus, by adjusting the number of the convolution capacitors arranged in parallel to one another and the capacitance of each of the convolution capacitors, it is possible to realize a sampling mixer capable of adjusting the number of notches and the notch frequency and easily eliminating a particular frequency component. ## Claims ### Claim 1 A discrete filter comprising: a control signal generator that generates a plurality of control signals of a same frequency and varying phases; a convolution capacity section that receives as input a received signal; a buffer capacitor that integrates a discrete signal released from the convolution capacity section, wherein: the convolution capacity section includes m+1 integration units including m integration elements connected in parallel (where m is a natural number of two or more); all of the m integration elements included in one integration unit selected from the m+1 integration units integrate the received signal at a same timing based on the control signals; and an integration element selected one by one from the m integration units other than the selected one integration unit, outputs a signal integrated earlier at a same timing at which the received signal is integrated. ### Claim 2 (depends on 1) The discrete filter according to claim 1, wherein: the m+1 integration units are connected in parallel; and the integration units including m integration elements that integrate the received signal switch to other integration units at timings based on the control signals. ### Claim 3 (depends on 2) The discrete filter according to claim 2, wherein: each integration unit comprises: integration switches that switch an inputted state of the received signal to the m integration units; and m release switches connected to each integration element; the integration switches are turned on in a cycle such that on states of the integration units do not overlap in a time domain; and them release switches in each integration unit are turned on in a cycle such that on states of the m release switches and on states of the integration switches provided in a same integration unit do not overlap in the time domain. ### Claim 4 (depends on 2) The discrete filter according to claim 2, further comprising: a signal reset section that resets the received signal integrated in the integration units; and a feedback switch that, after the received signal is reset, feeds back a feedback signal for adjusting output characteristics of the integration units, to the integration units. ### Claim 5 (depends on 2) The discrete filter according to claim 2, further comprising: a rotate capacitor that is provided between the integration units and the buffer capacitor; other integration switches that switch inputted states of released signals of the integration units to the rotate capacitor; and other release switches that are connected to one end of the rotate capacitor and that switch released states of signals to the buffer capacitor integrated in the rotate capacitor. ### Claim 6 (depends on 2) The discrete filter according to claim 2, further comprising a history capacitor with one end connected to input stages of the integration units. ### Claim 7 (depends on 2) The discrete filter according to claim 2, wherein the m+1 integration units connected in parallel are arranged in series. ### Claim 8 A discrete filter comprising: a first convolution capacity section that comprises m+1 integration units which comprises m integration elements connected in parallel and integrating a received signal (where m is a natural number of two or more) and which are connected in parallel; a second convolution capacity section that has a same configuration as the first convolution capacity section and that receives as input a received signal of a phase opposite to the received signal inputted to the first convolution capacity section; and a first buffer capacitor and a second buffer capacitor that integrate signals released from the first convolution capacity section and the second convolution capacity section, wherein: each integration unit of the first convolution capacity section releases the received signal integrated in the m integration elements to the second buffer capacitor at specific release timings out of m release timings associated with the m integration elements, and releases the received signal to the first buffer capacitor at release timings other than the specific release timings; and each integration unit of the second convolution capacity section releases the received signal integrated in the m integration elements to a buffer capacitor opposite to the integration units of the first convolution capacity section at same release timings as the integration units of the applicable first convolution capacity section. ### Claim 9 (depends on 8) The discrete filter according to claim 8, wherein the specific release timings comprising an even-numbered release timing out of the m release timings. ### Claim 10 (depends on 8) A discrete filter according to claim 8, wherein: each integration unit comprises: integration switches that switch an inputted state of the received signal to the N integration elements; and m release switches connected to each integration unit, in each integration unit of the first convolution capacity section, release switches that are turned on in even-numbered turns from timings at which states of the integration switches switch, are connected to the second buffer capacitor and release switches that are turned on in odd-numbered turns, are connected to the first buffer capacitor; and in each integration unit of the second convolution capacity section, release switches that are turned on in odd-number turns from timings at which states of the integration switches switch, are connected to the second buffer capacitor and release switches that are turned on in odd-number turns, are connected to the first buffer capacitor. ### Claim 11 (depends on 1) A sampling mixer comprising: a discrete filter according to claim 1; and a sampling switch that is provided at a stage prior to the discrete filter and that samples a received signal at a predetermined frequency. ### Claim 12 (depends on 8) A sampling mixer comprising: a discrete filter according to claim 8; and a sampling switch that is provided at a stage prior to the discrete filter and that samples a received signal at a predetermined frequency. ### Claim 13 (depends on 1) A radio apparatus comprising: a discrete filter according to claim 1; a signal processor that carries out signal processing based on an output signal of the discrete filter; and a modulator that modulates the output signal after the signal processing in the signal processor. ### Claim 14 (depends on 8) A radio apparatus comprising: a discrete filter according to claim 8; a signal processor that carries out signal processing based on an output signal of the discrete filter; and a modulator that modulates the output signal after the signal processing in the signal processor. ### Claim 15 (depends on 11) A radio apparatus comprising: a sampling mixer according to claim 11; a signal processor that carries out signal processing based on an output signal of the discrete filter; and a modulator that modulates the output signal after the signal processing in the signal processor. ### Claim 16 (depends on 12) A radio apparatus comprising: a sampling mixer according to claim 12; a signal processor that carries out signal processing based on an output signal of the discrete filter; and a modulator that modulates the output signal after the signal processing in the signal processor.