# US 2010/0167641 A1 · Power management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0167641 A1 - Document ID: US20100167641A1 - Status: Published application - Kind: A1 - Application number: 12/317,581 - Filed: 2008-12-26 - Published: 2010-07-01 - Earliest claimed: 2008-12-26 - Assignees: Nokia Corporation - Inventors: Jukka Tapio Virtanen - Web page: https://patentgrep.com/patent/US20100167641A1 ## CPC - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3209: Monitoring remote activity, e.g. over telephone lines or network connections - G06K 19/0701: {at least one of the integrated circuit chips comprising an arrangement for power management} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An apparatus, a method and a computer program, the apparatus including: an interface configured to detect a first electrical signal, the first electrical signal being provided by a transceiver; secure transaction circuitry having a first power state and a second power state, the secure transaction circuitry being configured, when in the second power state, to perform a transaction, using the transceiver, with a further apparatus; memory circuitry having power states; and control circuitry configured, in response to detecting the first electrical signal, to control the secure transaction circuitry to switch from being in the first power state to being in the second power state, without changing a power state of the memory circuitry. ## Claims ### Claim 1 An apparatus, comprising: secure transaction circuitry having a first power state and a second power state, the secure transaction circuitry being configured, when in the second power state, to perform a transaction, using a transceiver, with a further apparatus; memory circuitry having power states; and control circuitry configured to detect a first electrical signal provided by the transceiver and configured, in response to detecting the first electrical signal, to control the secure transaction circuitry to switch from being in the first power state to being in the second power state, without changing a power state of the memory circuitry. ### Claim 2 (depends on 1) An apparatus as claimed in claim 1, wherein the secure transaction circuitry is unable, when in the first power state, to perform a transaction with the further apparatus. ### Claim 3 (depends on 1) An apparatus as claimed in claim 1, wherein the first power state of the secure transaction circuitry is an off state or a standby state. ### Claim 4 (depends on 1) An apparatus as claimed in claim 1, wherein the memory circuitry has a first power state and a second power state, and wherein the control circuitry is configured, in response to detecting the first electrical signal, to switch the secure transaction circuitry from being in the first power state to being in the second power state without changing the memory circuitry from being in the first power state to being the second power state. ### Claim 5 (depends on 4) An apparatus as claimed in claim 4, wherein the memory circuitry is configured, when in the second power state, to be written to and read from, and the memory is unable, when in the first power state, to be written to and read from. ### Claim 6 (depends on 1) An apparatus as claimed in claims 1, wherein the first power state of the memory circuitry is an off state or a standby state. ### Claim 7 (depends on 1) An apparatus as claimed in claim 1, wherein the secure transaction circuitry comprises secure transaction memory circuitry, different to the memory circuitry, and the secure transaction memory circuitry stores transaction data for use in performing a transaction. ### Claim 8 (depends on 1) An apparatus as claimed in claim 1, wherein the secure transaction circuitry comprises a secure transaction controller, and the control circuitry is the secure transaction controller. ### Claim 9 (depends on 1) An apparatus as claimed in claims 1, wherein the secure transaction circuitry comprises a secure transaction controller, and the control circuitry is a memory controller, different to the secure transaction controller. ### Claim 10 (depends on 9) An apparatus as claimed in claim 9, wherein the memory controller is configured to control reading and writing of data to the memory circuitry. ### Claim 11 (depends on 1) An apparatus as claimed in claim 1, wherein the first electrical signal is a wakeup signal for instructing switching of the secure transaction circuitry from the first power state to the second power state. ### Claim 12 (depends on 1) An apparatus as claimed in claim 1, wherein the first electrical signal is provided in response to the transceiver detecting a wireless signal. ### Claim 13 (depends on 1) An apparatus as claimed in claim 1, wherein the transceiver is a near field communication transceiver. ### Claim 14 (depends on 1) An integrated circuit comprising an apparatus as claimed in claim 1. ### Claim 15 (depends on 1) An apparatus as claimed in claim 1, wherein the apparatus is a portable memory apparatus. ### Claim 16 (depends on 15) An electronic device comprising the portable memory apparatus as claimed in claim 15, the electronic device further comprising a receptacle configured to receive the portable memory apparatus. ### Claim 17 A method, comprising: detecting a first electrical signal provided by a transceiver; and switching, in response to detecting the first electrical signal, secure transaction circuitry of an apparatus from being in a first power state to being in a second power state, without switching a power state of memory circuitry of the apparatus, wherein when the secure transaction circuitry is in the second power state, it is configured to perform a transaction, using the transceiver, with a further apparatus. ### Claim 18 (depends on 17) A method as claimed in claim 17, wherein the secure transaction circuitry is unable, when in the first power state, to perform a transaction with the further apparatus. ### Claim 19 (depends on 17) A method as claimed in claim 17, wherein the memory circuitry has a first power state and a second power state, and the secure transaction circuitry is switched from being in the first power state to being in second power state without changing the memory circuitry from being in the first power state to being the second power state. ### Claim 20 (depends on 19) A method as claimed in claim 19, wherein the memory circuitry is able, when in the second power state, to be written to and read from, and the memory circuitry is unable, when in the first power state, to be written to and read from. ### Claim 21 A computer program comprising instructions which, when executed by a processor, enable: detecting a first electrical signal provided by a transceiver; and switching, in response to detecting the first electrical signal, secure transaction circuitry of an apparatus from being in a first power state to being in a second power state, without switching a power state of memory circuitry of the apparatus, wherein when the secure transaction circuitry is in the second power state, it is configured to perform a transaction, using the transceiver, with a further apparatus. ### Claim 22 (depends on 21) A computer program as claimed in claim 21, wherein the secure transaction circuitry is unable, when in the first power state, to perform a transaction with the further apparatus. ### Claim 23 (depends on 21) A computer program as claimed in claim 21, wherein the memory circuitry has a first power state and a second power state, and the secure transaction circuitry is switched from being in the first power state to being in second power state without changing the memory circuitry from being in the first power state to being the second power state. ### Claim 24 (depends on 23) A computer program as claimed in claim 23, wherein the memory circuitry is able, when in the second power state, to be written to and read from, and the memory circuitry is unable, when in the first power state, to be written to and read from. ### Claim 25 An apparatus, comprising: means for detecting a first electrical signal, the first electrical signal being provided by a transceiver; secure transaction means having a first power state and a second power state, the secure transaction means being for performing, when in the second power state, a transaction, using the transceiver, with a further apparatus; memory means having power states; and means for controlling, in response to detection of the first electrical signal, the secure transaction means to switch from being in the first power state to being in the second power state, without changing a power state of the memory means.