# US 2010/0167552 A1 · Methods for particle removal during integrated circuit device fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0167552 A1 - Document ID: US20100167552A1 - Status: Published application - Kind: A1 - Application number: 12/345,732 - Filed: 2008-12-30 - Published: 2010-07-01 - Earliest claimed: 2008-12-30 - Assignees: Texas Instruments Incorporated - Inventors: Murlidhar Bashyam; Rajneesh Jaiswal; Jason R. Heine - Web page: https://patentgrep.com/patent/US20100167552A1 ## CPC - H10P 70/234: {the processing being the formation of vias or contact holes} - H10P 72/0414: {using mainly spraying means, e.g. nozzles} - H10P 72/0434: {mainly by convection} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing an IC device includes providing a workpiece having least one dielectric layer disposed on a surface of the workpiece. The method also includes processing the dielectric layer to form a plurality of apertures in the dielectric layer, where the processing includes at least one micromask-prone process. The method further includes subsequent to the processing step, cryogenically treating the workpiece. In the method, the treating step removes particles deposited on or in the plurality of apertures during the processing step and maintains the plurality of apertures, where the particles are generated from micromask features resulting from the micromask-prone process. ## Claims ### Claim 1 A method of manufacturing an IC device, comprising: providing a workpiece having least one dielectric layer disposed on at least a portion of a surface of said workpiece; processing said dielectric layer to form a plurality of apertures in at least said dielectric layer, said processing comprising at least one micromask-prone process, and subsequent to said processing step, cryogenically treating said workpiece, wherein said treating step removes at least a portion of a plurality of particles deposited on or in said plurality of apertures during said processing step and maintains said plurality of apertures, wherein said plurality of particles are generated from micromask features resulting from said micromask-prone process. ### Claim 2 (depends on 1) The method of claim 1, wherein said cryogenically treating step further comprises: introducing said workpiece into a cryogenic treatment chamber having at least one nozzle, said nozzle having at least one orifice aimed at an angle of impingement toward said surface of said workpiece; and directing a cryogenic aerosol from said orifice onto said surface of said workpiece, wherein a kinetic energy of said aerosol fluid is sufficient to dislodge said portion of said plurality of particles deposited on or in said plurality of apertures. ### Claim 3 (depends on 2) The method of claim 2, wherein said directing further comprises discharging a cryogenic fluid from said orifice, said cryogenic fluid comprising at least one of argon, nitrogen, and carbon dioxide. ### Claim 4 (depends on 1) The method of claim 1, wherein said dielectric layer comprises at least one of an undoped silicate glass layer, a phosphosilicate glass layer, a borophosphosilicate glass layer, a silicon nitride layer (SiNx), and a silicon oxide (SiOx) layer disposed on said surface of said workpiece. ### Claim 5 (depends on 4) The method of claim 4, wherein said treating step further maintains a chemical mechanical polishing (CMP) resistance of said dielectric layer. ### Claim 6 (depends on 4) The method of claim 4, wherein said treating step maintains a thickness of said dielectric layer. ### Claim 7 (depends on 4) The method of claim 4, wherein said treating step maintains one or more dimensions of said plurality of apertures. ### Claim 8 (depends on 1) The method of claim 1, wherein said micromask-prone process comprises at least one of a planarization process, a lithography process, an etch process, and a post-etch cleaning process. ### Claim 9 A method of manufacturing an integrated circuit (IC), comprising: providing a substrate having a semiconducting surface; forming a plurality of devices on or in said semiconducting surface; depositing at least one dielectric contact layer over said semiconducting surface; processing said dielectric contact layer to form a plurality of apertures in said dielectric contact layer for forming contacts to said plurality of devices, said processing comprising at least one micromask-prone process; and subsequent to said processing step, cryogenically treating said dielectric contact layer; wherein said treating step removes at least a portion of a plurality of particles deposited on or in said plurality of apertures during said processing step and maintains said plurality of apertures, wherein said plurality of particles are generated from micromask features resulting from said micromask-prone process. ### Claim 10 (depends on 9) The method of claim 9, wherein said cryogenically treating further comprises: introducing said substrate into a cryogenic treatment chamber having at least one nozzle, said nozzle having at least one orifice aimed at an angle of impingement toward said substrate; and directing a cryogenic aerosol from said orifice onto said dielectric contact layer, wherein a kinetic energy of said aerosol fluid is sufficient to dislodge said portion of said plurality of particles deposited on or in said plurality of apertures. ### Claim 11 (depends on 10) The method of claim 10, wherein said directing further comprises discharging a cryogenic fluid from said orifice, said cryogenic fluid comprising at least one of argon and nitrogen. ### Claim 12 (depends on 9) The method of claim 9, wherein said dielectric contact layer comprises at least one of an undoped silicate glass layer, a phosphosilicate glass layer, and a borophosphosilicate glass layer. ### Claim 13 (depends on 12) The method of claim 12, wherein said treating step further maintains a chemical mechanical polishing (CMP) resistance of said dielectric contact layer. ### Claim 14 (depends on 12) The method of claim 12, wherein said treating step maintains a thickness of said dielectric contact layer. ### Claim 15 (depends on 12) The method of claim 12, wherein said treating step maintains one or more dimensions of said plurality of apertures. ### Claim 16 (depends on 9) The method of claim 9, wherein said micromask-prone process comprises at least one of a planarization process, a lithography process, an etch process, and a post-etch cleaning process. ### Claim 17 A method of manufacturing an integrated circuit (IC), comprising: providing a substrate having a semiconducting surface; depositing at least one dielectric masking layer over a portion of said semiconducting surface; processing said dielectric masking layer to form a plurality of apertures in said dielectric masking layer and said semiconducting surface, said processing comprising at least one micromask-prone process; and subsequent to said processing step, cryogenically treating said substrate; wherein said treating step removes at least a portion of a plurality of particles deposited on or in said plurality of apertures during said processing step and maintains said plurality of apertures, wherein said plurality of particles are generated from micromask features resulting from said etch process, and wherein said micromask-prone process comprises at least one of a lithography process, an etch process, and a post-etch cleaning process. ### Claim 18 (depends on 17) The method of claim 17, wherein said treating step further comprises: introducing said substrate into a cryogenic treatment chamber having at least one nozzle, said nozzle having at least one orifice aimed at an angle of impingement toward said substrate; and directing a cryogenic aerosol from said orifice onto said dielectric contact layer, wherein a kinetic energy of said aerosol fluid is sufficient to dislodge said portion of said plurality of particles deposited on or in said plurality of apertures. ### Claim 19 (depends on 17) The method of claim 17, wherein said treating step maintains a thickness of said dielectric masking layer. ### Claim 20 (depends on 17) The method of claim 17, wherein said treating step maintains one or more dimensions of said plurality of apertures in said dielectric masking layer and said semiconducting surface.