# US 2010/0167495 A1 · Semiconductor device manufacturing method, semiconductor device and wafer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2010/0167495 A1
- Document ID: US20100167495A1
- Status: Published application
- Kind: A1
- Application number: 12/718,047
- Filed: 2010-03-05
- Published: 2010-07-01
- Earliest claimed: 2005-08-26
- Assignees: Honda Motor Co., Ltd.
- Inventors: Nobuaki Miyakawa; Takanori Maebashi; Takahiro Kimura
- Web page: https://patentgrep.com/patent/US20100167495A1

## CPC

- H10W 90/00: Package configurations
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members}
- H10W 90/20: Configurations of stacked chips
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

## Claims

### Claim 1

A semiconductor device manufacturing method comprising the steps of:
forming a first trench in a main surface of the wafer, and then forming a through isolation portion by burying a first insulating film in the first trench;
forming an element on the main surface of the wafer;
forming a second trench within a region surrounded by the through isolation portion on the main surface of the wafer, and then forming a through interconnect portion electrically connected to a semiconductor circuit unit of another wafer by burying a conductive film in the second trench; and
making the wafer thinner to an extent not to reach to the through isolation portion and the through interconnect portion from an undersurface of the wafer, and then etching from the undersurface of the wafer until parts of the through isolation portion and the through interconnect portion are exposed.

### Claim 2 (depends on 1)

The semiconductor device manufacturing method according to claim 1, wherein the step of forming the through isolation portion includes a step of forming an insulating film in the first trench through thermal oxidation, and the element is formed after the through isolation portion is formed.

### Claim 3 (depends on 1)

The semiconductor device manufacturing method according to claim 1, further comprising:
a step of forming the element on the main surface of the wafer and then depositing a second insulating film on the main surface of the wafer so as to cover the element;
a step of forming the second trench extending from an upper surface of the second insulating film to a position within a thickness of the wafer; and
a step of burying the conductive film in the second trench to form the through interconnect portion.

### Claim 4 (depends on 1)

The semiconductor device manufacturing method according to claim 1, wherein the conductive film is made of metal.

### Claim 5 (depends on 1)

The semiconductor device manufacturing method according to claim 1, wherein the step of making the wafer thinner to the extent not to reach the through isolation portion and the through interconnect portion is performed through either one of grinding, polishing, and both of grinding and polishing.

### Claim 6

A semiconductor device manufacturing method comprising the steps of:
preparing a plurality of wafers;
forming a semiconductor circuit unit on each of the plurality of wafers;
laminating the plurality of wafers together and electrically connecting the semiconductor circuit units on the plurality of wafers to each other; and
after the step of laminating the plurality of wafers together, cutting the plurality of wafers into chips each having a three-dimensional configuration with a plurality of chips being stacked together, wherein
a step of forming an upper wafer of the plurality of wafers comprising the steps of:
forming a first trench in a main surface of the upper wafer, and then forming a through isolation portion by burying a first insulating film in the first trench;
forming an element on the main surface of the upper wafer;
forming a second trench within a region surrounded by the through isolation portion on the main surface of the upper wafer, and then forming a through interconnect portion electrically connected to a semiconductor circuit unit of another wafer of the plurality of wafers by burying a conductive film in the second trench; and
making the upper wafer thinner to an extent not to reach to the through isolation portion and the through interconnect portion from an undersurface of the upper wafer, and then etching from the undersurface of the upper wafer until parts of the through isolation portion and the through interconnect portion are exposed.

### Claim 7 (depends on 6)

The semiconductor device manufacturing method according to claim 6, wherein the step of making the wafer thinner to the extent not to reach to the through isolation portion and the through interconnect portion is performed through either one of grinding, polishing, and both of grinding and polishing.

### Claim 8

A semiconductor device manufacturing method comprising the steps of:
preparing a plurality of wafers;
forming a semiconductor circuit unit on each of the plurality of wafers;
laminating the plurality of wafers together and electrically connecting the semiconductor circuit units on the plurality of wafers to each other; and
after the step of laminating the plurality of wafers together, cutting the plurality of wafers into chips each having a three-dimensional configuration with a plurality of chips being stacked together, wherein
a step of forming an upper wafer of the plurality of wafers, the step of forming the upper wafer comprising the steps of:
forming a first trench in a main surface of the upper wafer, and then forming a through isolation portion by burying a first insulating film in the first trench;
forming an element on the main surface of the upper wafer;
forming a second trench within a region surrounded by the through isolation portion on the main surface of the upper wafer, and then forming a through interconnect portion electrically connected to a semiconductor circuit unit of another wafer of the plurality of wafers by burying a conductive film in the second trench; and
exposing parts of the through isolation portion and the through interconnect portion from an undersurface of the upper wafer,
a step of forming a lower wafer of the plurality of wafers comprising the steps of:
forming an element configuring the semiconductor circuit unit on a main surface of the lower wafer; and
forming a bump on the main surface of the lower wafer, the bump being electrically connected to the semiconductor circuit unit of the lower wafer, and
a step of electrically connecting the semiconductor circuit units of the plurality of wafers by jointing the through interconnect portion exposed from the undersurface of the upper wafer of the plurality of wafers and the bump on the main surface of the lower wafer of the plurality of wafers, with the through interconnect portion and the bump being in contact with each other.

### Claim 9 (depends on 8)

The semiconductor device manufacturing method according to claim 8, wherein the step of exposing parts of the through isolation portion and the through interconnect portion from the undersurface of the upper wafer comprises a step of making the upper wafer thinner to an extent not to reach to the through isolation portion and the through interconnect portion from an undersurface of the upper wafer, and then etching from the undersurface of the upper wafer until parts of the through isolation portion and the through interconnect portion are exposed.

### Claim 10 (depends on 9)

The semiconductor device manufacturing method according to claim 9, wherein the step of making the wafer thinner to the extent not to reach the through isolation portion and the through interconnect portion is performed through either one of grinding, polishing, and both of grinding and polishing.

### Claim 11 (depends on 6)

The semiconductor device manufacturing method according to claim 6, wherein the step of forming the through isolation portion includes a step of forming an insulating film in the first trench through thermal oxidation, and the element is formed after the through isolation portion is formed on the main surface of the upper wafer.

### Claim 12 (depends on 6)

The semiconductor device manufacturing method according to claim 6, further comprising:
a step of forming the element on the main surface of the upper wafer and then depositing a second insulating film on the main surface of the upper wafer so as to cover the element;
a step of forming the second trench extending from an upper surface of the second insulating film to a position within a thickness of the upper wafer; and
a step of burying the conductive film in the second trench to form the through interconnect portion.

### Claim 13 (depends on 6)

The semiconductor device manufacturing method according to claim 6, wherein the conductive film is made of metal.