# US 2010/0167491 A1 · Method for fabricating flash memory device

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- Number: US 2010/0167491 A1
- Document ID: US20100167491A1
- Status: Published application
- Kind: A1
- Application number: 12/637,003
- Filed: 2009-12-14
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Inventors: Min-Gon Lee
- Web page: https://patentgrep.com/patent/US20100167491A1

## CPC

- H10B 41/30: characterised by the memory core region
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method for fabricating a flash memory device includes forming device isolation films in a semiconductor substrate, defining active regions between the device isolation films, and patterning floating gates on the semiconductor substrate to correspond to the active regions. Portions where the active regions and the floating gates are not overlap with one another are within reference offset ranges, respectively.

## Claims

### Claim 1

A method comprising:
forming device isolation films in a semiconductor substrate and defining active regions between the device isolation films; and then
patterning floating gates over the semiconductor substrate to correspond to the active regions,
wherein portions where the active regions and the floating gates are not overlapped with one another are within reference offset ranges, respectively.

### Claim 2 (depends on 1)

The method of claim 1, wherein each floating gate is patterned to overlap only with the active region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the active region is defined to have a first area and the floating gates are patterned such that an area of each floating gate not overlapping with the active region is within the reference offset range.

### Claim 4 (depends on 3)

The method of claim 3, wherein when the active region is defined to have the first area, each floating gate is patterned to overlap only with the active region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the floating gate is defined to have a second area and the device isolation films are formed such that the active regions each have an area not overlapped with the floating gate being within the reference offset range.

### Claim 6 (depends on 5)

The method of claim 5, wherein when each floating gate is defined to have a second area, the device isolation films are formed such that the active regions overlap entirely with the floating gates.

### Claim 7 (depends on 3)

The method of claim 3, wherein patterning the floating gates comprises:
forming polysilicon over the semiconductor substrate having the active regions each with the first area;
forming a first photoresist pattern over the polysilicon; and then
etching the polysilicon using the first photoresist pattern as a mask to pattern the floating gate.

### Claim 8 (depends on 1)

The method of claim 1, wherein defining the active regions comprises:
defining the active regions each to have a first area between the device isolation films.

### Claim 9 (depends on 8)

The method of claim 8, wherein patterning the floating gate comprises:
patterning the floating gates over the semiconductor substrate such that each floating gate has a second area corresponding to a respective active region.

### Claim 10 (depends on 9)

The method of claim 9, wherein a portion where the active region defined to have the first area and the floating gate patterned to have the second area do not overlap is within the reference offset range.

### Claim 11 (depends on 10)

The method of claim 10, wherein the active regions defined to have the first areas and the floating gates patterned to have the second areas are matched such that the active regions and the floating gates entirely overlap with one another.

### Claim 12

A method comprising:
forming device isolation films in a semiconductor substrate to define active regions in the semiconductor substrate located between the device isolation films; and then
forming polysilicon over the semiconductor substrate;
forming a first photoresist pattern over the polysilicon; and then
forming floating gates over the semiconductor substrate corresponding to the active regions by etching the polysilicon using the first photoresist pattern as a mask,
wherein the floating gates where the active regions and the floating gates are not overlapped with one another are within reference offset ranges, respectively.

### Claim 13 (depends on 12)

The method of claim 12, wherein defining the active regions comprises:
defining the active regions each to have a first area between the device isolation films.

### Claim 14 (depends on 12)

The method of claim 12, wherein the active region is defined to have a first area and the floating gates are patterned such that an area of each floating gate not overlapping with the active region is within the reference offset range.

### Claim 15

A method comprising:
forming device isolation films in a semiconductor substrate and defining active regions between the device isolation films to have a first area; and then
patterning floating gates over the semiconductor substrate to correspond to the active regions,
wherein portions where the active regions and the floating gates are not overlapped with one another are within reference offset ranges, respectively.

### Claim 16 (depends on 15)

The method of claim 15, wherein patterning the floating gates comprises:
forming polysilicon over the semiconductor substrate having the active regions;
forming a first photoresist pattern over the polysilicon; and then
etching the polysilicon using the first photoresist pattern as a mask.

### Claim 17 (depends on 15)

The method of claim 15, wherein the floating gates are patterned such that an area of each floating gate not overlapping with the active region is within the reference offset range.

### Claim 18 (depends on 15)

The method of claim 15, wherein patterning the floating gate comprises:
patterning the floating gates over the semiconductor substrate such that each floating gate has a second area corresponding to a respective active region.

### Claim 19 (depends on 15)

The method of claim 15, wherein a portion where the active region defined to have the first area and the floating gate patterned to have the second area do not overlap is within the reference offset range.

### Claim 20 (depends on 1)

The method of claim 1, wherein the floating gate is defined to have a second area and the device isolation films are formed such that the active regions each have an area not overlapped with the floating gate being within the reference offset range.