# US 2010/0167490 A1 · Method of Fabricating Flash Memory Device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0167490 A1 - Document ID: US20100167490A1 - Status: Published application - Kind: A1 - Application number: 12/629,920 - Filed: 2009-12-03 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Jong-wan Choi; Yong-soon Choi; Bo-young Lee; Eunkee Hong; Eun-kyung Baek; Ju-seon Goo - Web page: https://patentgrep.com/patent/US20100167490A1 ## CPC - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed. ## Claims ### Claim 1 A method of fabricating a flash memory device, the method comprising: forming gate lines comprising a series of a plurality of cell gate lines and a plurality selection gate lines, each comprising a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, formed on a semiconductor substrate; forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the plurality of cell gate lines and the plurality of selection gate lines, and does not fill a space located on outer sides of the plurality of selection gate lines that are opposite the plurality of cell gate lines; forming a spacer on the outer sides of the plurality of selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer; and forming a second insulating layer in a space where the spacer is formed. ### Claim 2 (depends on 1) The method of claim 1, further comprising forming a diffusion barrier on the plurality of gate lines, before forming the first insulating layer. ### Claim 3 (depends on 1) The method of claim 1, wherein the first insulating layer is formed in a chemical vapor deposition (CVD) method using octamethyleyclotetrasiloxane (OMCTS) or tetramethylorthosilicate (TMOS) as a source material. ### Claim 4 (depends on 1) The method of claim 1, wherein forming the first insulating layer is performed at a deposition temperature of about 0° C. to 100° C. and a deposition pressure of about 0.5 Torr to 100 Torr. ### Claim 5 (depends on 1) The method of claim 1, wherein the first insulating layer includes a Si—O—H bonding or a Si—N—H bonding. ### Claim 6 (depends on 1) The method of claim 1, wherein the first insulating layer has a dielectric constant of about 1 to 3.5. ### Claim 7 (depends on 1) The method of claim 1, wherein the spacer is formed of a moderate temperature oxide (MTO) silicon oxide layer and/or a tetraethyl orthosilicate (TEOS) silicon oxide layer. ### Claim 8 (depends on 1) The method of claim 1, further comprising forming an etch stop layer, after forming the spacer and before forming the second insulating layer. ### Claim 9 (depends on 1) The method of claim 1, wherein the second insulating layer includes a high-density plasma (HDP) oxide layer. ### Claim 10 (depends on 1) The method of claim 1, further comprising: removing the hard mask layer of the gate lines; removing some parts of the first insulating layer, the second insulating layer, and the spacer so that at least a part of upper and side surfaces of the polysilicon layer for a control gate in the gate lines is exposed; forming a metal silicide on the exposed portion of the polysilicon layer for the control gate; and forming a third insulating layer on the semiconductor substrate on which the metal silicide is formed. ### Claim 11 A method of fabricating a flash memory device, the method comprising: forming gate lines comprising a plurality of cell gate lines and a selection gate line, each comprising a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, formed on a semiconductor substrate; forming a first insulating layer that selectively fills gaps between ones of the cell gate lines from the bottom up and gaps between a first side of the selection gate line and an adjacent one of the plurality of cell gate lines, and does not fill a space on a second side of the selection gate line that is opposite the first side of the selection gate line; forming a spacer on the second side of the selection gate line after forming the first insulating layer; and forming a second insulating layer in a space where the spacer is formed. ### Claim 12 (depends on 11) The method of claim 11, further comprising forming a diffusion barrier on the gate lines, before forming the first insulating layer. ### Claim 13 (depends on 11) The method of claim 11, wherein the first insulating layer is formed in a chemical vapor deposition (CVD) method using octamethyleyclotetrasiloxane (OMCTS) or tetramethylorthosilicate (TMOS) as a source material. ### Claim 14 (depends on 13) The method of claim 13, wherein forming the first insulating layer is performed at a deposition temperature of about 0° C. to 100° C. and a deposition pressure of about 0.5 Torr to 100 Torr. ### Claim 15 (depends on 11) The method of claim 11, wherein the first insulating layer includes a Si—O—H bonding or a Si—N—H bonding. ### Claim 16 (depends on 15) The method of claim 15, wherein the first insulating layer has a dielectric constant of about 1 to 3.5. ### Claim 17 (depends on 11) The method of claim 11, wherein the spacer is formed of a moderate temperature oxide (MTO) silicon oxide layer and/or a tetraethyl orthosilicate (TEOS) silicon oxide layer. ### Claim 18 (depends on 11) The method of claim 11, further comprising forming an etch stop layer, after forming the spacer and before forming the second insulating layer.