# US 2010/0167487 A1 · Mask rom devices and methods for forming the same

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- Number: US 2010/0167487 A1
- Document ID: US20100167487A1
- Status: Published application
- Kind: A1
- Application number: 12/723,265
- Filed: 2010-03-12
- Published: 2010-07-01
- Earliest claimed: 2007-01-26
- Inventors: Myung-Jo Chun; Hee-Seong Jeon; Yong-Kyu Lee; Young-Ho Kim
- Web page: https://patentgrep.com/patent/US20100167487A1

## CPC

- H10B 20/65: {of memory structures of the ROM only type}
- H10B 20/00: Read-only memory [ROM] devices
- H10B 20/387: {Source region or drain region doping programmed}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 30/0212: {using self-aligned silicidation}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

## Claims

### Claim 1

A method of forming a NOR type mask read only memory (MROM) device, comprising:
forming first and second gate electrodes at an on-cell region and an off-cell region of a cell region of a substrate, respectively, and third and fourth gate electrodes at first and second transistor regions of a logic circuit region of the substrate;
implanting impurities of a second conductivity type under a surface of the substrate located at both sides of the first and second gate electrodes to form a third impurity region adjacent the first gate electrode and a fourth impurity region adjacent the second gate electrode;
implanting impurities of a first conductivity type into the on-cell region located at both sides of the first gate electrode and into the first transistor region located at both sides of the third gate electrode to form first doping regions adjacent the first and third gate electrodes;
forming first, second, third, and fourth spacers on sidewalls of the first, second, third, and fourth gate electrodes, respectively;
implanting impurities of the first conductivity type into a substrate between the first, second, and third spacers to form second doping regions extending from corresponding first doping regions and spaced apart from the corresponding gate electrode at the on-cell region of the cell region and at the first transistor region of the logic circuit region, and to form a second impurity region at the off-cell region, the first and second doping regions at the on-cell region constituting a first impurity region and the first and second doping regions at the first transistor region constituting a fifth impurity region; and
implanting impurities of the second conductivity type into the second transistor region of the logic circuit region to form a sixth impurity region.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming an interlayer insulating layer at the substrate to cover the first, second, third, and fourth gate electrodes;
etching a portion of the interlayer insulating layer to form a contact hole exposing at least one region of the first, second, third, fourth, fifth, and sixth impurity regions; and
filling an inside of the contact hole with a conductive material to form a contact.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first, second, third, and fourth gate electrodes include polysilicon doped with an impurity.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a metal silicide pattern on the first, second, third, and fourth gate electrodes and a substrate located at a side portion of the first, second, third, and fourth spacers, respectively.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the first doping regions comprises:
forming an ion implantation mask pattern to cover the off-cell region and the second transistor region; and
implanting the first conductivity type impurities into the on-cell region and the first transistor region exposed by the ion implantation mask pattern.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
implanting the first conductivity type impurities into the logic circuit region to form a channel region before forming the fourth gate electrode.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the third and fourth impurity region comprises:
forming an ion implantation mask pattern to cover the logic circuit region;
implanting the second conductivity type impurities into the on-cell and off-cell regions.

### Claim 8 (depends on 1)

The method of claim 1, wherein a depth of the first doping region is shallower than those of both the third impurity region and the fourth impurity region.

### Claim 9 (depends on 1)

The method of claim 1, wherein a depth of the second doping region is shallower than those of both the third impurity region and the fourth impurity region.

### Claim 10 (depends on 1)

The method of claim 1, wherein a depth of the second doping region is deeper than that of first doping region.

### Claim 11 (depends on 1)

The method of claim 1, wherein a concentration of the second doping region is higher than that of the first doping region.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
implanting impurities of a second conductivity type under a surface of the substrate located at both sides of the fourth gate electrode to form a third doping region adjacent the fourth gate electrode.

### Claim 13 (depends on 12)

The method of claim 12, wherein a depth of the third doping region is shallower than that of the sixth impurity region.

### Claim 14 (depends on 12)

The method of claim 12, wherein the third doping region is formed before forming the spacers.