# US 2010/0167486 A1 · Method of fabricating transistor for semiconductor device

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- Number: US 2010/0167486 A1
- Document ID: US20100167486A1
- Status: Published application
- Kind: A1
- Application number: 12/492,939
- Filed: 2009-06-26
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Assignees: Hynix Semiconductor Inc.
- Inventors: Min-Jung Shin
- Web page: https://patentgrep.com/patent/US20100167486A1

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.

## Claims

### Claim 1

A method of fabricating a transistor in a semiconductor device, the method comprising:
forming a gate structure over a substrate;
forming a first trench by etching the substrate on a side of the gate structure to a first depth;
ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench;
etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench; and
growing an epitaxial layer within the second trench.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, after forming the first trench:
forming a material layer over a resulting structure; and
anisotropically etching the material layer to form a material spacer in the trench and a sidewall of the gate structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein the material spacer comprises a nitride layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising, after forming the source/drain region,
tilted-ion-implanting dopants of a second conductivity type different from the first conductivity type to form a counter doping region over the surface of the source/drain region.

### Claim 5 (depends on 1)

The method of claim 1, wherein the transistor is a PMOS transistor, and the first conductivity type is a P-type.

### Claim 6 (depends on 4)

The method of claim 4, wherein the transistor is a PMOS transistor, and the first conductivity type and the second conductivity are a P-type and an N-type, respectively.

### Claim 7 (depends on 1)

The method of claim 1, wherein the substrate comprises a Si substrate, and the epitaxial layer comprises a SiGe epitaxial layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein forming the source/drain region comprises performing a thermal treatment after the ion implantation of the dopants of the first conductivity type.

### Claim 9 (depends on 1)

The method of claim 1, wherein the dopants of the first conductivity type are doped in-situ while growing the epitaxial layer.

### Claim 10

A method of fabricating a transistor in a semiconductor device, the method comprising:
forming an isolation layer defining an active region on a substrate;
forming a gate structure over the substrate having the isolation layer;
etching a portion of the active region between the gate structure and the isolation layer to form a first trench to a first depth;
forming a material layer over the resulting substrate structure;
etching the material layer to partially expose the substrate covered by the material layer and leave a discontinuous layer of the material spacer over a sidewall of the gate structure and a sidewall of the isolation layer; and
after forming a source/drain region underneath the first trench, etching the substrate underneath the first trench to a second depth larger than the first depth to form a second trench.

### Claim 11 (depends on 10)

The method of claim 10, wherein the material spacer comprises a nitride layer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising, after forming the source/drain region,
tilted-ion-implanting dopants to form a counter doping region over the surface of the source/drain region.

### Claim 13 (depends on 10)

The method of claim 10, wherein the transistor is a PMOS transistor.

### Claim 14 (depends on 10)

The method of claim 10, further comprising growing an epitaxial layer within the second trench.