# US 2010/0167485 A1 · Contact Barrier Structure and Manufacturing Methods

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- Number: US 2010/0167485 A1
- Document ID: US20100167485A1
- Status: Published application
- Kind: A1
- Application number: 12/722,247
- Filed: 2010-03-11
- Published: 2010-07-01
- Earliest claimed: 2007-05-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ching-Ya Wang; Chung-Hu Ke; Wen-Chin Lee
- Web page: https://patentgrep.com/patent/US20100167485A1

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0215: {using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/034: {bottomless barrier, adhesion or liner layers}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
forming a silicon-containing component;
forming a metal layer on the silicon-containing component;
reacting the metal layer with the silicon-containing component to form a silicide region, wherein a top portion of the metal layer is not consumed by the step of reacting;
forming a contact over and electrically connected to the top portion of the metal layer; and
forming a contact barrier layer at least encircling the contact.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of forming the metal layer comprises blanket formation, and wherein the method further comprises:
selectively removing a first portion of the top portion of the metal layer, wherein a second portion of the top portion of the metal layer directly underlying the contact remains after the selective removal.

### Claim 3 (depends on 1)

The method of claim 1, wherein the step of forming the metal layer comprises blanket formation, and wherein the method further comprises:
before the step of reacting, selectively removing a first portion of the metal layer, wherein a second portion of the metal layer directly underlying the contact remains after the selective removal.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second portion of the metal layer covers only a portion of the silicon-containing component.

### Claim 5 (depends on 1)

The method of claim 1, wherein the step of forming the metal layer comprises selectively depositing the metal layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the selective depositing comprises depositing using atomic layer deposition.

### Claim 7 (depends on 5)

The method of claim 5, wherein the selective depositing comprises electroless plating.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
forming an inter-layer dielectric (ILD) over the silicon-containing component;
forming an opening in the ILD; and
before the step of forming the contact in the opening, forming the contact barrier layer in the opening.

### Claim 9 (depends on 8)

The method of claim 8, wherein the contact barrier layer partially covers a bottom of the opening.

### Claim 10 (depends on 8)

The method of claim 8, wherein the contact comprises copper.

### Claim 11

A method of forming a semiconductor structure, the method comprising:
providing a semiconductor substrate;
forming a gate dielectric over the semiconductor substrate;
forming a gate electrode over the gate dielectric;
forming a source/drain region adjacent the gate dielectric;
forming a metal layer covering at least the source/drain region;
reacting only a bottom portion of the metal layer with the source/drain region to form a silicide region, wherein a top portion of the metal layer remains after the step of reacting;
forming an inter-layer dielectric (ILD) over the silicide region and the gate electrode;
forming a contact in the ILD, wherein the contact is fully situated over, and electrically and directly connected to, the top portion of the metal layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the step of forming the metal layer comprises a blanket formation, and wherein the method further comprises:
selectively removing a first portion of the top portion of the metal layer, wherein a second portion of the top portion of the metal layer directly over the source/drain region remains after the selective removal.

### Claim 13 (depends on 11)

The method of claim 11, wherein the step of forming the metal layer comprises blanket formation, and wherein the method further comprises:
before the step of reacting, selectively removing a first portion of the metal layer, wherein a second portion of the metal layer directly underlying the contact remains after the selective removal.

### Claim 14 (depends on 12)

The method of claim 12, wherein the second portion of the top portion of the metal layer covers only a portion of the source/drain region.

### Claim 15 (depends on 11)

The method of claim 11, wherein the step of forming the metal layer comprises selective deposition.

### Claim 16 (depends on 15)

The method of claim 15, wherein the selective deposition comprises atomic layer deposition.

### Claim 17 (depends on 15)

The method of claim 15, wherein the selective deposition comprises electroless plating.

### Claim 18 (depends on 11)

The method of claim 11, wherein the step of forming the contact further comprises forming an opening in the ILD, and wherein the method further comprises forming a contact barrier layer in the opening before the step of forming the contact.

### Claim 19 (depends on 18)

The method of claim 18, wherein the contact barrier layer only partially covers a bottom of the opening.