# US 2010/0167481 A1 · Manufacturing process of a vertical-conduction misfet device with gate dielectric structure having differentiated thickness and vertical-conduction misfet device thus manufacture

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- Number: US 2010/0167481 A1
- Document ID: US20100167481A1
- Status: Published application
- Kind: A1
- Application number: 12/721,685
- Filed: 2010-03-11
- Published: 2010-07-01
- Earliest claimed: 2007-03-02
- Assignees: STMicroelectronics S.r.I.
- Inventors: Orazio Battiato; Domenico Repici; Fabrizio Marco Di Paola; Giuseppe Arena; Angelo Magri'
- Web page: https://patentgrep.com/patent/US20100167481A1

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/662: {having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 62/152: {Source regions of DMOS transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.

## Claims

### Claim 1

A process for manufacturing a vertical MISFET device comprising:
in a semiconductor wafer, forming a semiconductor layer having a first type of conductivity and a first level of doping;
in the semiconductor layer, making at least a first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity;
forming an enriched region in the semiconductor layer between the first body region and the second body region, the enriched region having the first type of conductivity and a second level of doping, higher than the first level of doping;
forming a gate electrode extending over the enriched region, over part of the first body region and over part of the second body region; and
forming a dielectric gate structure between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first body region and the second body region;
wherein forming the enriched region comprises:
forming a first conductive layer on the semiconductor layer;
forming an enrichment opening in the first conductive layer; and
introducing a dopant species into the semiconductor layer through the enrichment opening;
and in that forming a dielectric gate structure comprises filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.

### Claim 2 (depends on 1)

The process according to claim 1, wherein filling the enrichment opening comprises:
depositing a dielectric filling layer; and
removing a portion of the dielectric filling layer that exceeds the enrichment opening.

### Claim 3 (depends on 2)

The process according to claim 2, wherein removing comprises planarizing the wafer by CMP.

### Claim 4 (depends on 2)

The process according to claim 2, wherein removing comprises etching the wafer by plasma etching.

### Claim 5 (depends on 2)

The process according to claim 2, comprising forming a sacrificial layer on the first conductive layer prior to forming the enrichment opening and wherein the step of removing is stopped at the sacrificial layer.

### Claim 6 (depends on 5)

The process according to claim 5, wherein removing comprises eliminating residue of the dielectric filling layer by wet etch.

### Claim 7 (depends on 5)

The process according to claim 5, comprising removing the sacrificial layer.

### Claim 8 (depends on 1)

The process according to claim 1, wherein forming the dielectric gate structure comprises forming a dielectric gate layer on the semiconductor layer.

### Claim 9 (depends on 8)

The process according to claim 8, wherein forming the enrichment opening comprises selectively etching the first conductive layer and stopping etching of the first conductive layer at the dielectric gate layer.

### Claim 10 (depends on 9)

The process according to claim 9, wherein the first conductive layer is anisotropically etched.

### Claim 11 (depends on 1)

The process according claim 1, wherein forming the gate electrode comprises:
depositing a second conductive layer directly in contact with the first conductive layer; and
shaping the first conductive layer and the second conductive layer.

### Claim 12 (depends on 11)

The process according to claim 11, wherein depositing the second conductive layer comprises coating the dielectric gate structure.

### Claim 13 (depends on 1)

The process according to claim 1, wherein filling the enrichment opening comprises forming a thick dielectric gate region in the enrichment opening.

### Claim 14 (depends on 13)

The process according to claim 13, wherein forming the enrichment opening comprises using a first mask and forming the first body region and the second body region comprises etching the first conductive layer using a second mask having body openings at the side of the enriched region and coating the thick dielectric gate region.

### Claim 15 (depends on 13)

The process according to claim 13, wherein walls of the thick dielectric gate region form an angle greater than 70° with a surface of the semiconductor layer.

### Claim 16 (depends on 1)

The process according to claim 1, wherein forming the gate electrode comprises:
depositing a second conductive layer directly in contact with the first conductive layer;
forming a protective dielectric layer on the conductive layer; and
shaping, by a single mask, the protective dielectric layer, the second conductive layer and the first conductive layer.

### Claim 17 (depends on 16)

The process according to claim 16, comprising:
forming an insulating structure after shaping the protective dielectric layer, the second conductive layer, and the first conductive layer; and
performing an unmasked anisotropic etch of the insulating structure.

### Claim 18 (depends on 17)

The process according to claim 17, wherein forming the insulating structure comprises:
forming a silicon-nitride layer having a thickness comprised between 10 nm and 100 nm; and
forming a silicon-oxide layer having a thickness comprised between 100 nm and 600 nm.

### Claim at position 19

-41. (canceled)

### Claim 42

A method, comprising:
forming a first body region having a first conductivity in a semiconductor layer having a first level of a second conductivity;
forming in the semiconductor layer an adjust region having a second level of the second conductivity;
forming over the first body region a first portion of a gate insulator having a first thickness; and
forming over the adjust region a second portion of the gate insulator having a second thickness.

### Claim 43 (depends on 42)

The method of claim 42, further comprising forming the semiconductor layer by epitaxially growing the semiconductor layer over a substrate.

### Claim 44 (depends on 42)

The method of claim 42 wherein forming the first body region comprises forming the first body region spaced apart from the adjust region.

### Claim 45 (depends on 42)

The method of claim 42, further comprising forming in the first body region a source region having the second conductivity.

### Claim 46 (depends on 42)

The method of claim 42, further comprising forming a gate over the gate insulator.

### Claim 47 (depends on 42)

The method of claim 42, further comprising:
forming in the semiconductor layer a second body region having the first conductivity; and
forming over the second body region a third region of the gate insulator having substantially the first thickness.

### Claim 48 (depends on 47)

The method of claim 47, further comprising forming in the second body region a source region having the second conductivity.