# US 2010/0167477 A1 · Localized temperature control during rapid thermal anneal

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2010/0167477 A1
- Document ID: US20100167477A1
- Status: Published application
- Kind: A1
- Application number: 12/719,153
- Filed: 2010-03-08
- Published: 2010-07-01
- Earliest claimed: 2007-02-26
- Assignees: International Business Machines Corporation
- Inventors: Brent A. Anderson; Edward J. Nowak
- Web page: https://patentgrep.com/patent/US20100167477A1

## CPC

- H10P 34/422: {using incoherent radiation}
- H10W 10/0124: {the regions having non-rectangular shapes, e.g. rounded (H10W10/0123 takes precedence)}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such devices. Selectively controlling the temperature changes in different devices during a rapid thermal anneal is accomplished by selectively varying the isolation material thickness in different sections of a shallow trench isolation structures. Alternatively, it is accomplished by selectively varying the pattern of fill structures in different sections of a semiconductor wafer so that predetermined amounts of shallow trench isolation regions in the different sections are exposed.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
providing a substrate;
forming on a first section of said substrate at least one first device, a first isolation region adjacent to said first device, and fill structures adjacent to said first isolation region; and
simultaneously forming on a second section of said substrate at least one second device, a second isolation region adjacent to said second device and said fill structures adjacent to said second isolation region,
wherein a first pattern of said fill structures in said first section is such that a first amount of an isolation material in said first isolation region is exposed and wherein a second pattern of said fill structures in said second section is such that a second amount of said isolation material in said second isolation region is exposed.

### Claim 2 (depends on 1)

The method of claim 1, wherein said forming of said fill structures comprises at least one of the following:
forming single crystalline semiconductor structures adjacent to said first isolation region and said second isolation region;
forming polycrystalline semiconductor structures above said first isolation region and said second isolation region; and
forming dielectric structures above said first isolation region and said second isolation region.

### Claim 3 (depends on 2)

The method of claim 2, wherein said forming of said single crystalline semiconductor structures comprises forming dummy devices in said first section and said second section

### Claim 4 (depends on 2)

The method of claim 2, wherein said forming of said polycrystalline semiconductor structures comprises forming dummy polysilicon gate structures in said first section and said second section

### Claim 5 (depends on 2)

The method of claim 2, wherein said forming of said dielectric structures comprises forming and patterning one of an oxide layer, a nitride layer and an oxide-nitride stack in said first section and said second section.

### Claim 6 (depends on 1)

The method of claim 1, further comprising predetermining said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section so that said first device and said second device achieve predetermined maximum temperatures during a single rapid thermal anneal.

### Claim 7 (depends on 6)

The method of claim 6, wherein said predetermined maximum temperatures are different optimal dopant activation temperatures for said first device and said second device.

### Claim 8 (depends on 1)

The method of claim 1, further comprising predetermining said first amount and said second amount so that said performance characteristics exhibited by said first device and said second device are different.

### Claim 9

A method of forming a semiconductor structure comprising:
providing a substrate;
forming on a first section of said substrate at least one first device, a first isolation region adjacent to said first device, and fill structures adjacent to said first isolation region; and
simultaneously forming on a second section of said substrate at least one second device, a second isolation region adjacent to said second device and said fill structures adjacent to said second isolation region,
wherein a first pattern of said fill structures in said first section is such that a first amount of an isolation material in said first isolation region is exposed and wherein a second pattern of said fill structures in said second section is such that a second amount of said isolation material in said second isolation region is exposed, and
wherein said forming of said fill structures comprises forming a surplus of fill structures such that some of said fill structures can be selectively removed in order to form said first pattern and said second pattern.

### Claim 10 (depends on 9)

The method of claim 9, wherein said forming of said fill structures comprises at least one of the following:
forming single crystalline semiconductor structures adjacent to said first isolation region and said second isolation region;
forming polycrystalline semiconductor structures above said first isolation region and said second isolation region; and
forming dielectric structures above said first isolation region and said second isolation region.

### Claim 11 (depends on 9)

The method of claim 9, wherein said forming of said single crystalline semiconductor structures comprises forming dummy devices in said first section and said second section

### Claim 12 (depends on 9)

The method of claim 9, wherein said forming of said polycrystalline semiconductor structures comprises forming dummy polysilicon gate structures in said first section and said second section

### Claim 13 (depends on 9)

The method of claim 9, wherein said forming of said dielectric structures comprises forming and patterning one of an oxide layer, a nitride layer and an oxide-nitride stack in said first section and said second section.

### Claim 14 (depends on 9)

The method of claim 9, further comprising predetermining said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section so that said first device and said second device achieve predetermined maximum temperatures during a single rapid thermal anneal.

### Claim 15 (depends on 9)

The method of claim 9, wherein said predetermined maximum temperatures are different optimal dopant activation temperatures for said first device and said second device.

### Claim 16 (depends on 9)

The method of claim 9, further comprising predetermining said first amount and said second amount so that said performance characteristics exhibited by said first device and said second device are different.

### Claim 17

A method of forming a semiconductor structure comprising:
providing a substrate;
forming on a first section of said substrate at least one first device, a first isolation region adjacent to said first device, and fill structures adjacent to said first isolation region;
simultaneously forming on a second section of said substrate at least one second device, a second isolation region adjacent to said second device and said fill structures adjacent to said second isolation region, wherein a first pattern of said fill structures in said first section is such that a first amount of an isolation material in said first isolation region is exposed and wherein a second pattern of said fill structures in said second section is such that a second amount of said isolation material in said second isolation region is exposed; and
predetermining said first amount of said isolation material exposed in said first section and said second amount of said isolation material exposed in said second section so that said first device and said second device exhibit predetermined performance characteristics following a rapid thermal anneal.

### Claim 18 (depends on 17)

The method of claim 17, wherein said forming of said fill structures comprises at least one of the following:
forming single crystalline semiconductor structures adjacent to said first isolation region and said second isolation region;
forming polycrystalline semiconductor structures above said first isolation region and said second isolation region; and
forming dielectric structures above said first isolation region and said second isolation region.

### Claim 19 (depends on 17)

The method of claim 17, wherein said forming of said single crystalline semiconductor structures comprises forming dummy devices in said first section and said second section

### Claim 20 (depends on 17)

The method of claim 17, wherein said forming of said polycrystalline semiconductor structures comprises forming dummy polysilicon gate structures in said first section and said second section