# US 2010/0167472 A1 · Implantation shadowing effect reduction using thermal bake process

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2010/0167472 A1
- Document ID: US20100167472A1
- Status: Published application
- Kind: A1
- Application number: 12/646,479
- Filed: 2009-12-23
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Texas Instruments Incorporated
- Inventors: Yiming Gu; Shaofeng Yu; James Blatchford
- Web page: https://patentgrep.com/patent/US20100167472A1

## CPC

- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- G03F 7/40: Treatment after imagewise removal, e.g. baking
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body. A second bake of the developed selectively exposed resist layer is then performed, thereby rounding the corner edge of the resist feature.

## Claims

### Claim 1

A method of forming a resist feature, comprising:
forming a resist layer over a semiconductor body;
selectively exposing the resist layer;
performing a first bake of the selectively exposed resist layer;
developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body;
performing a second bake of the developed selectively exposed resist layer, thereby rounding the corner edge of the resist feature.

### Claim 2 (depends on 1)

The method of claim 1, wherein the resist layer has a melting point associated therewith, wherein a temperature of the second bake is less than the melting point of the resist coating.

### Claim 3 (depends on 2)

The method of claim 2, wherein the temperature of the second bake is greater than a temperature of the first bake.

### Claim 4 (depends on 1)

The method of claim 1, further comprising performing a trim process after developing the selectively exposed resist layer to reduce a height of the resist feature.

### Claim 5 (depends on 4)

The method of claim 4, wherein the trim process is performed before the second bake.

### Claim 6 (depends on 1)

The method of claim 1, further comprising performing a vapor phase priming of a surface of the semiconductor body prior to forming the resist layer thereon, thereby improving an adhesion of the resist layer to the semiconductor body surface.

### Claim 7

A method of forming a resist structure, comprising:
forming a chemical amplified deep ultraviolet resist layer over a semiconductor body surface;
patterning the resist layer to form a resist feature having a corner edge; and
rounding the corner edge of the resist structure with a bake process.

### Claim 8 (depends on 7)

The method of claim 7, further comprising performing a post-exposure bake process after the patterning of the resist layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein a temperature of the bake process employed to round the corner edge of the resist feature is greater than a temperature of the post-exposure bake process.

### Claim 10 (depends on 7)

The method of claim 7, wherein a temperature of the bake process is less than the melting point of the resist layer.

### Claim 11 (depends on 7)

The method of claim 7, further comprising performing a vapor phase priming of a surface of the semiconductor body prior to forming the resist layer thereon, thereby improving an adhesion of the resist layer to the semiconductor body surface.

### Claim 12 (depends on 7)

The method of claim 7, further comprising performing a trim process after developing the selectively exposed resist layer to reduce a height of the resist feature.

### Claim 13 (depends on 12)

The method of claim 12, wherein the trim process is performed before the bake process.

### Claim 14

A method of forming a semiconductor device, comprising:
forming an active area of a first conductivity type within a semiconductor body of a second conductivity type;
forming a gate structure in the active area;
forming a resist layer over the gate structure and the active area;
patterning the resist layer to expose the gate structure and at least a portion of the active area, the patterned resist layer having a corner edge;
rounding the corner edge of the patterned resist layer with a bake process; and
implanting dopant at a non-perpendicular angle with respect to a surface of the active area into the exposed portion of the active area.

### Claim 15 (depends on 14)

The method of claim 14, wherein the dopant is of the first conductivity type and forms a pocket implant region.

### Claim 16 (depends on 14)

The method of claim 14, further comprising performing a trim process after developing the selectively exposed resist layer to reduce a height of the resist feature.

### Claim 17 (depends on 16)

The method of claim 16, wherein the trim process is performed before the second bake.

### Claim 18 (depends on 14)

The method of claim 14, wherein the resist layer has a melting point associated therewith, wherein a temperature of the second bake is less than the melting point of the resist coating.

### Claim 19 (depends on 14)

The method of claim 14, further comprising performing a post-exposure bake process after the patterning of the resist layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein a temperature of the bake process employed to round the corner edge of the resist feature is greater than a temperature of the post-exposure bake process.