# US 2010/0167430 A1 · Apparatus and method for testing a transducer and/or electronic circuitry associated with a transducer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0167430 A1 - Document ID: US20100167430A1 - Status: Published application - Kind: A1 - Application number: 12/649,596 - Filed: 2009-12-30 - Published: 2010-07-01 - Earliest claimed: 2008-12-30 - Inventors: Colin Findlay Steele; John Laurence Pennock - Web page: https://patentgrep.com/patent/US20100167430A1 ## CPC - G01R 31/2829: {Testing of circuits in sensor or actuator systems (testing of apparatus for measuring electric or magnetic variables G01R35/00; testing of indicating or recording apparatus G01D; in airbag systems B60R21/0173; checking gas analysers G01N33/007; monitoring or fail-safe circuits for electromagnets H01F7/1844)} - G01R 31/312: by capacitive methods - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W 90/753: {between laterally-adjacent chips} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method and apparatus for applying a test signal to a node of a signal path of an integrated circuit using a parasitic capacitance of the integrated circuit associated with the node. For example, a parasitic capacitance associated with a bond pad may be used to apply a test signal to a signal path. Alternatively, a parasitic capacitance associated with a shielding element may be used to apply a test signal to the signal path. ## Claims ### Claim 1 An integrated circuit having a signal path, the integrated circuit comprising: means for coupling a test signal to a node of the signal path via a parasitic capacitance of the integrated circuit associated with the node. ### Claim 2 (depends on 1) An integrated circuit as claimed in claim 1, further comprising a conductive region associated with the parasitic capacitance, wherein the means for coupling the test signal is configured to couple the test signal to the parasitic capacitance using the conductive region. ### Claim 3 (depends on 1) An integrated circuit as claimed in claim 1, wherein the conductive region is a shielding element associated with the signal path. ### Claim 4 (depends on 1) An integrated circuit as claimed in claim 1, wherein the conductive region is a region of n-type or p-type semiconductor material. ### Claim 5 (depends on 1) An integrated circuit as claimed in claim 1, further comprising switching means for selectively coupling the test signal to the node via the parasitic capacitance. ### Claim 6 (depends on 5) An integrated circuit as claimed in claim 5, wherein the switching means is configured to selectively couple a reference voltage to the parasitic capacitance during a non-test mode of operation. ### Claim 7 (depends on 6) An integrated circuit as claimed in claim 6, wherein the reference voltage is a ground reference voltage. ### Claim 8 (depends on 1) An integrated circuit as claimed in claim 1, further comprising a signal source for generating the test signal. ### Claim 9 (depends on 8) An integrated circuit as claimed in claim 8, wherein the signal source is adapted to provide a test signal having a variable frequency and/or amplitude. ### Claim 10 (depends on 1) An integrated circuit as claimed in claim 1, wherein the node comprises a bond pad. ### Claim 11 (depends on 1) An integrated circuit as claimed in claim 1, wherein the node is an input terminal of an amplifier suitable for connection to a capacitive transducer. ### Claim 12 (depends on 1) An integrated circuit as claimed in claim 1 wherein the integrated circuit is configured to process a signal associated with a capacitive transducer. ### Claim 13 A method of applying a test signal to a node of a signal path of an integrated circuit, the method comprising the steps of: coupling a test signal to the node via a parasitic capacitance of the integrated circuit associated with the node. ### Claim 14 (depends on 13) A method as claimed in claim 13, wherein the step of coupling the test signal comprises the step of coupling the test signal via a conductive region associated with the parasitic capacitance. ### Claim 15 (depends on 13) A method as claimed in claim 13, wherein the conductive region is a shielding element associated with the signal path. ### Claim 16 (depends on 13) A method as claimed in claim 13, wherein the conductive region is a region of n-type or p-type semiconductor material. ### Claim 17 (depends on 13) A method as claimed in claim 13, further comprising the step of providing switching means, and operating the switching means to selectively couple the test signal to the node via the parasitic capacitance. ### Claim 18 (depends on 17) A method as claimed in claim 17, further comprising the step of selectively coupling a reference voltage to the parasitic capacitance during a non-test mode of operation. ### Claim 19 (depends on 18) A method as claimed in claim 18, wherein the reference voltage is a ground reference voltage. ### Claim 20 (depends on 13) A method as claimed in claim 13, further comprising the steps of varying the frequency and/or amplitude of the test signal during a test mode of operation. ### Claim 21 (depends on 13) A method as claimed in claim 13, wherein the method is performed on a parasitic capacitance associated with a bond pad. ### Claim 22 (depends on 13) A method as claimed in claim 13, wherein the method is performed on a node of an input terminal of an amplifier suitable for connection to a capacitive transducer. ### Claim 23 (depends on 13) A method of testing an assembly comprising a first integrated circuit (100) comprising a capacitive transducer and a second integrated circuit (102) comprising associated electronic circuitry, the method comprising the steps of: mounting the first integrated circuit and the second integrated circuit on a common substrate; and testing the first integrated circuit and/or the second integrated circuit using the method as defined in claim 13 prior to the step of electrically connecting the first integrated circuit and the second integrated circuit. ### Claim 24 (depends on 13) A method of testing an assembly comprising a first integrated circuit (100) comprising a capacitive transducer and a second integrated circuit (102) comprising associated electronic circuitry, the method comprising the steps of: mounting the first integrated circuit and the second integrated circuit on a common substrate; electrically connecting the first integrated circuit and the second integrated circuit; and testing the first integrated circuit and/or the second integrated circuit using the method as defined in claim 13. ### Claim 25 (depends on 24) A method as claimed in claim 24, wherein the method comprises the step of testing the continuity of one or more interconnection points between the first integrated circuit and the second integrated circuit. ### Claim 26 (depends on 24) A method as claimed in claim 24, wherein the method comprises the step of testing the function of the capacitive transducer on the first integrated circuit (100). ### Claim 27 (depends on 24) A method as claimed in claim 24, wherein the method comprises the step of testing the function of an amplifier provided on the second integrated circuit. ### Claim 28 (depends on 13, 23) A method as claimed in claim 23, further comprising the steps of: packaging the first integrated circuit and the second integrated circuit; and testing the first integrated circuit and/or the second integrated circuit using the method as defined in claim 13. ### Claim 29 (depends on 12) A device as claimed in claim 12 wherein the device is at least one of; a MEMS devices; an ultrasound imager; a sonar transmitter; a sonar receiver; a mobile phone; a personal desktop assistant; an MP3 player; and a laptop.