# US 2010/0166173 A1 · Subscriber line interface circuitry with integrated serial interfaces

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- Number: US 2010/0166173 A1
- Document ID: US20100166173A1
- Status: Published application
- Kind: A1
- Application number: 12/347,994
- Filed: 2008-12-31
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Inventors: Xun Yang; Jeffrey A. Whaley; Joel W. Page; Chester Yu; Gregory James Fyke
- Web page: https://patentgrep.com/patent/US20100166173A1

## CPC

- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04J 14/0247: {Sharing one wavelength for at least a group of ONUs}
- H04J 14/0252: {Sharing one wavelength for at least a group of ONUs, e.g. for transmissions from-ONU-to-OLT or from-ONU-to-ONU}
- H04Q 11/0067: {Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring}
- H04J 14/0226: {Fixed carrier allocation, e.g. according to service}
- H04J 14/0282: {WDM tree architectures}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W)

## Abstract

Methods and apparatus for communicating include coupling first and second devices with a first unidirectional data line, a second unidirectional data line, and a clock line. Frames of data are serially communicated between the first and second devices using the first and second unidirectional data lines. The frame format of a frame carried by the first unidirectional data line is distinct from a frame format of a frame carried by the second unidirectional data line. Each frame is synchronized with a clock signal carried by the clock line.

## Claims

### Claim 1

A method of communicating comprising:
a) coupling a first device and a second device with a first unidirectional data line carrying data from the first device to the second device, a second unidirectional data line carrying data from the second device to the first device, and a clock line carrying a clock signal from the first device to the second device; and
b) communicating frames of data serially between the first and second devices using the first and second unidirectional data lines, wherein frames communicated on the first unidirectional line have a first frame format, wherein frames communicated on the second unidirectional line have a second frame format, wherein individual timeslots of frames of the first and second formats are communicated substantially synchronously to the clock signal, wherein the first and second frame formats are distinct.

### Claim 2 (depends on 1)

The method of claim 1 wherein the second device is a subscriber line interface circuit.

### Claim 3 (depends on 1)

The method of claim 1 wherein the first device is a gateway for an optical network.

### Claim 4 (depends on 1)

The method of claim 1 wherein the first frame format includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the first frame format includes at least one CS value and at least one SDI value from an SPI interface of the first device, wherein the clock signal is a multiple of a PCLK associated with a PCM interface of the first device.

### Claim 5 (depends on 1)

The method of claim 1 wherein the second frame format includes a DTX value from a PCM interface of the second device, wherein the second frame format includes at least one SDO value from an SPI interface of the second device.

### Claim 6 (depends on 1)

The method of claim 1 wherein the first frame format includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the first frame format includes at least one CS value and at least one SDI value from an SPI interface of the first device, wherein the clock signal is a multiple of a PCLK associated with a PCM interface of the first device, wherein the second frame format includes a DTX value from a PCM interface of the second device and at least one SDO value from an SPI interface of the second device.

### Claim 7 (depends on 6)

The apparatus of claim 6 wherein the first frame carries an SDI_V bit for each SDI value and the second frame carries an SDO_V bit for each SDO value to qualify the validity of the SDI and SDO bits, respectively.

### Claim 8 (depends on 1)

The method of claim 1 wherein the first device is an optical network gateway, wherein the second device is a SLIC, wherein the first frame format includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the first frame format includes at least one CS value and at least one SDI value from an SPI interface of the first device, wherein the clock signal is a multiple of a PCLK associated with a PCM interface of the first device, wherein the second frame format includes a DTX value from a PCM interface of the second device and at least one SDO value from an SPI interface of the second device.

### Claim 9

A communication apparatus, comprising:
a first device;
a second device coupled to the first device with a first unidirectional data line, a second unidirectional data line, and a clock line;
wherein frames of data are serially communicated between the first and second devices using the first and second unidirectional data lines, wherein frames communicated on the first unidirectional line have a first frame format, wherein frames communicated on the second unidirectional line have a second frame format, wherein each frame is synchronized with the clock signal, wherein the first and second frame formats are distinct.

### Claim 10 (depends on 9)

The apparatus of claim 9 wherein the second device is a subscriber line interface circuit.

### Claim 11 (depends on 9)

The apparatus of claim 9 wherein the first device is an optical network gateway.

### Claim 12 (depends on 9)

The apparatus of claim 9 wherein the first frame format includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the first frame format includes a first and second CS value and a first and second SDI value from an SPI interface of the first device, wherein the clock signal is a multiple of a PCLK associated with a PCM interface of the first device.

### Claim 13 (depends on 9)

The apparatus of claim 9 wherein the second frame format includes a DTX value from a PCM interface of the second device and at least one SDO value from an SPI interface of the second device.

### Claim 14 (depends on 9)

The apparatus of claim 9 wherein the first frame format includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the first frame format includes at least one CS value and at least one SDI value from an SPI interface of the first device, wherein the clock signal is a multiple of a PCLK associated with a PCM interface of the first device, wherein the second frame format includes a DTX value from a PCM interface of the second device and at least one SDO value from an SPI interface of the second device.

### Claim 15 (depends on 14)

The apparatus of claim 14 wherein the first frame carries an SDI_V bit for each SDI value and the second frame carries an SDO_V bit for each SDO value to qualify the validity of the SDI and SDO bits, respectively.

### Claim 16 (depends on 9)

The apparatus of claim 9 wherein the first device is an optical network gateway, wherein the second device is a SLIC, the first frame format includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the first frame format includes at least one CS value and at least one SDI value from an SPI interface of the first device, wherein the clock signal is a multiple of a PCLK associated with a PCM interface of the first device, wherein the second frame format includes a DTX value from a PCM interface of the second device and at least one SDO value from an SPI interface of the second device.