# US 2010/0166136 A1 · Shift register circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0166136 A1 - Document ID: US20100166136A1 - Status: Published application - Kind: A1 - Application number: 12/647,108 - Filed: 2009-12-24 - Published: 2010-07-01 - Earliest claimed: 2008-12-25 - Assignees: Mitsubishi Electric Corporation - Inventors: Youichi TOBITA - Web page: https://patentgrep.com/patent/US20100166136A1 ## CPC - G11C 19/184: {with field-effect transistors, e.g. MOS-FET} - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2330/021: Power management, e.g. power saving - G11C: STATIC STORES (semiconductor memory devices H10B) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal. ## Claims ### Claim 1 A shift register circuit comprising: an input terminal; an output terminal; a clock terminal; a first transistor for charging said output terminal by providing a constant first power supply potential to said output terminal; a second transistor for discharging said output terminal; a pull-up driving circuit for driving said first transistor; and a pull-down driving circuit for driving said second transistor, wherein said pull-up driving circuit includes: a third transistor for providing a clock signal provided at said clock terminal to a first node connected to a control electrode of said first transistor; and a boosting circuit for increasing a potential at said first node, wherein a control electrode of said third transistor is charged when an input signal input to said input terminal is activated, and the control electrode of said third transistor is discharged when said first node is charged by activation of the clock signal, wherein said pull-down driving circuit discharges a control electrode of said second transistor before the charging of said first node by activation of the clock signal begins, and wherein said boosting circuit increases the potential at said first node after the control electrode of said third transistor is discharged. ### Claim 2 (depends on 1) The shift register circuit according to claim 1, wherein said boosting circuit includes a first capacitive element whose one end is connected to said first node, and increases the potential at said first node by charging said second node connected to the other end of said first capacitive element. ### Claim 3 (depends on 2) The shift register circuit according to claim 2, wherein said boosting circuit charges said second node by providing to said second node a second power supply potential larger in absolute value than the first power supply potential. ### Claim 4 (depends on 2) The shift register circuit according to claim 2, wherein said boosting circuit includes a bootstrap circuit containing a load transistor for charging said second node and having a control electrode connected to said first node, and a potential at the control electrode of said load transistor is increased by said first capacitive element in accordance with charging of said second node. ### Claim 5 (depends on 2) The shift register circuit according to claim 2, wherein said boosting circuit includes a bootstrap circuit containing a load transistor for charging said second node and a second capacitive element connected between a control electrode of said load transistor and said second node, and a potential at the control electrode of said load transistor is increased by said second capacitive element in accordance with charging of said second node. ### Claim 6 (depends on 1) The shift register circuit according to claim 1 further comprising a fourth transistor for discharging said output terminal when a reset signal input to a predetermined reset terminal is activated. ### Claim 7 (depends on 6) The shift register circuit according to claim 6, wherein said pull-down driving circuit discharges the control electrode of said second transistor when the input signal is activated, and charges the control electrode of said second transistor when the reset signal is activated. ### Claim 8 (depends on 1) The shift register circuit according to claim 1 further comprising a fourth transistor for discharging said output terminal, wherein another clock signal having a phase different from the clock signal input to said clock terminal is provided to a control electrode of said fourth transistor during at least an activated period of an output signal output from said output terminal. ### Claim 9 (depends on 8) The shift register circuit according to claim 8, wherein said pull-down driving circuit discharges the control electrode of said second transistor when the input signal is activated, and charges the control electrode of said second transistor when a signal provided to the control electrode of said fourth transistor is activated. ### Claim 10 (depends on 1) The shift register circuit according to claim 1, wherein said pull-up driving circuit further includes a fifth transistor connected between said first node and said clock terminal and having a control electrode connected to said output terminal. ### Claim 11 (depends on 1) The shift register circuit according to claim 1, further including a sixth transistor connected between said output terminal and said clock terminal and having a control electrode connected to said input terminal. ### Claim 12 (depends on 1) A multiple-stage shift register circuit including a plurality of cascade-connected shift register circuits, wherein each stage of said multiple-stage shift register circuit is the shift register circuit according to claim 1, and further comprises a switching circuit receiving an output signal from a preceding stage and an output signal from a subsequent stage and capable of switching which of the output signal received from said preceding stage and the output signal received from said subsequent stage is provided to said input terminal. ### Claim 13 A shift register circuit comprising: an input terminal; an output terminal; a clock terminal; a first transistor for charging said output terminal by providing a constant first power supply potential to said output terminal; and a pull-up driving circuit for driving said first transistor; wherein said pull-up driving circuit includes: a second transistor for charging a first node by providing a second power supply potential larger in absolute value than the first power supply potential to said first node connected to a control electrode of said first transistor; a third transistor for providing a clock signal provided at said clock terminal to a second node connected to a control node of said second transistor; and a boosting circuit for boosting said second node, wherein a control electrode of said third transistor is charged when an input signal input to said input terminal is activated, and the control electrode of said third transistor is discharged when said second node is charged by activation of the clock signal, and wherein said boosting circuit increases the potential at said second node after the control electrode of said third transistor is discharged. ### Claim 14 (depends on 13) The shift register circuit according to claim 13 further including a fifth transistor providing the clock signal to said first node and having a control electrode connected to the control electrode of said third transistor. ### Claim 15 (depends on 13) The shift register circuit according to claim 13, wherein said boosting circuit includes a first capacitive element whose one end is connected to said second node, and increases the potential at said second node by charging a third node connected to the other end of said first capacitive element. ### Claim 16 (depends on 15) The shift register circuit according to claim 15, wherein said boosting circuit charges said third node by providing the second power supply potential to said third node. ### Claim 17 (depends on 15) The shift register circuit according to claim 15, wherein said boosting circuit includes a bootstrap circuit containing a load transistor for charging said third node and having a control electrode connected to said second node, and a potential at the control electrode of said load transistor is increased by said first capacitive element in accordance with charging of said third node. ### Claim 18 (depends on 15) The shift register circuit according to claim 15, wherein said boosting circuit includes a bootstrap circuit containing a load transistor for charging said third node and a second capacitive element connected between a control electrode of said load transistor and said third node, and a potential at the control electrode of said load transistor is increased by said second capacitive element in accordance with charging of said third node. ### Claim 19 (depends on 13) The shift register circuit according to claim 13 further comprising a fourth transistor for discharging said output terminal when a reset signal input to a predetermined reset terminal is activated. ### Claim 20 (depends on 19) The shift register circuit according to claim 19 further comprising: a fifth transistor for discharging said output terminal; and a pull-down driving circuit for driving the fifth transistor, wherein said pull-down driving circuit discharges a control electrode of said fifth transistor when the input signal is activated, and charges the control electrode of said fifth transistor when the reset signal is activated. ### Claim 21 (depends on 13) The shift register circuit according to claim 13 further comprising a fourth transistor for discharging said output terminal, wherein another clock signal having a phase different from the clock signal input to said clock terminal is provided to a control electrode of said fourth transistor during at least an activated period of an output signal output from said output terminal. ### Claim 22 (depends on 21) The shift register circuit according to claim 21 further comprising: a fifth transistor for discharging said output terminal; and a pull-down driving circuit for driving the fifth transistor, wherein said pull-down driving circuit discharges a control electrode of said fifth transistor when the input signal is activated, and discharges the control electrode of said fifth transistor when a signal provided to the control electrode of said fourth transistor is activated. ### Claim 23 (depends on 13) The shift register circuit according to claim 13, wherein said pull-up driving circuit further includes a sixth transistor connected between said first node and said clock terminal and having a control electrode connected to said output terminal. ### Claim 24 (depends on 13) The shift register circuit according to claim 13, further including a seventh transistor connected between said output terminal and said clock terminal and having a control electrode connected to said input terminal. ### Claim 25 (depends on 13) A multiple-stage shift register circuit including a plurality of cascade-connected shift register circuits, wherein each stage of said multiple-stage shift register circuit is the shift register circuit according to claim 13, and further comprises a switching circuit receiving an output signal from a preceding stage and an output signal from a subsequent stage and capable of switching which of the output signal received from said preceding stage and the output signal received from said subsequent stage is provided to said input terminal.