# US 2010/0166132 A1 · Pll/dll dual loop data synchronization

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- Number: US 2010/0166132 A1
- Document ID: US20100166132A1
- Status: Published application
- Kind: A1
- Application number: 12/719,450
- Filed: 2010-03-08
- Published: 2010-07-01
- Earliest claimed: 2000-12-20
- Assignees: Infineon Technologies Austria AG
- Inventors: BENJAMIM TANG; Scott Southwell; Nicholas Robert Steffen
- Web page: https://patentgrep.com/patent/US20100166132A1

## CPC

- H04J 3/047: {Distributors with transistors or integrated circuits}
- H04J 3/062: {Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers (pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06)}
- H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

## Claims

### Claim at position 1

1-54. (canceled)

### Claim 55

A plesiochronous data retiming method comprising:
recovering a clock from a received serial input data at a digital delay-locked loop (DDLL);
deserializing said serial data to a parallel data using said recovered clock;
writing said parallel data to a first-in-first-out register (FIFO);
synthesizing a transmit clock;
reading said parallel data from said FIFO;
serializing said parallel data using said synthesized transmit clock;
detecting a FIFO fill level at a delay-locked loop (DLL); and
phase shifting, in a phase-locked loop (PLL), an output of a VCO, wherein said phase shifting is in response to said detecting step.

### Claim 56 (depends on 55)

The retiming method of claim 55, wherein said synthesizing step comprises phase locking said VCO to a local reference.

### Claim 57 (depends on 55)

The retiming method of claim 55, further comprising translating said FIFO fill level to an integrating value.

### Claim 58 (depends on 55)

The retiming method of claim 55, wherein said writing step and said reading step comprise a write clock of said FIFO and a read clock of said FIFO, respectively.

### Claim 59 (depends on 58)

The retiming method of claim 58, further comprising phase locking said write and read clocks of said FIFO in said DLL.

### Claim 60 (depends on 58)

The retiming method of claim 58, further comprising locking said VCO output to said FIFO write clock.

### Claim 61

In a plesiochronous system, a method for PLL/DLL data serialization comprising:
detecting a local reference at a phase/frequency detector (PFD) of a phase-locked loop (PLL);
phase locking a voltage-controlled oscillator (VCO) of said PLL to a local reference to suppress a phase noise of said VCO;
receiving a parallel data input and a data clock at a first-in-first-out register (FIFO);
filtering, at a delay-locked loop (DLL), a signal representative of a fill level of said FIFO;
phase shifting an output of said VCO of said PLL in response to said filtering step;
locking said PLL to a frequency corresponding to a pre-filtered signal input to said DLL;
receiving, at a parallel-in serial-out (PISO) serializer, said parallel data and said VCO output; and
outputting a serialized data from said PISO serializer with said VCO outputting a transmit clock.

### Claim 62 (depends on 61)

The method of claim 61, further comprising the step of outputting a synthesized clock.

### Claim 63 (depends on 61)

The method of claim 61, wherein said PLL filtering step comprises wide bandwidth filtering.

### Claim 64 (depends on 61)

The method of claim 61, wherein said DLL filtering step comprises narrow bandwidth filtering.

### Claim 65 (depends on 61)

The method of claim 61, further comprising the step of translating said signal in said DLL to a digital value.

### Claim 66 (depends on 61)

The method of claim 61, wherein said translating step comprises a phase detector in said DLL.

### Claim 67

A plesiochronous data retimer comprising:
a digital delay-locked loop (DDLL) receiving an input data to be retimed and configured to recover a clock of said input data;
a phase/frequency detector (PFD) receiving a local reference;
a phase shifter configured in a feedback loop with said PFD;
a first loop filter coupled to said phase shifter;
said phase/frequency detector (PFD), phase shifter and first loop filter forming a phase-locked loop, a serial-in and parallel-out (SIPO) deserializer coupled to said input data;
a first-in-first-out register (FIFO) coupled to said deserializer;
and a parallel-in serial-out (PISO) serializer receiving said deserialized input data and transmitting a serialized data.

### Claim 68 (depends on 67)

The retimer of claim 67, wherein said DDLL comprises a phase detector and a digital loop filter.

### Claim 69 (depends on 67)

The retimer of claim 67, wherein said DDLL comprises a wide bandwidth.

### Claim 70 (depends on 67)

The retimer of claim 67, further comprising a second loop filter.

### Claim 71 (depends on 69)

The retimer of claim 69, further comprising a dual bandwidth.