# US 2010/0166084 A1 · Nonlinearity robust successive requantizer

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- Number: US 2010/0166084 A1
- Document ID: US20100166084A1
- Status: Published application
- Kind: A1
- Application number: 12/579,899
- Filed: 2009-10-15
- Published: 2010-07-01
- Earliest claimed: 2008-10-15
- Assignees: The Regents of the University of California
- Inventors: Ian Galton; Ashok Swaminathan
- Web page: https://patentgrep.com/patent/US20100166084A1

## CPC

- H03M 7/3002: {Conversion to or from differential modulation}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An embodiment of the invention is a successive requantizer, which serves as a replacement for a ΔΣ modulator in a fractional-N PLL or a DAC, and avoids the above-mentioned spurious tone problem, thereby circumventing the tradeoffs that result from reliance on common approach of making highly linear analog circuitry to avoid spurious tones. A successive requantizer fractional-N PLL of the invention has the potential to reduce power consumption and the cost of commercial communication devices. A successive requantizer of the invention performs digital quantization one bit at a time in such a way that the quantization noise can be engineered to have desirable properties such as non-linearity robustness. The invention is applicable to most high-performance digital communication systems, such as cellular telephone handsets and wireless local and metropolitan area network transceivers.

## Claims

### Claim 1

A successive requantizer device comprising:
a plurality of quantization stages that each accept an input sequence and quantize the input sequence by a predetermined number of bits; wherein
each quantization stage generates a quantization sequence sd[n], with the property that xd+[n]+sd[n] is an even number for each n, where xd[n] is the quantization stage's input sequence; and
each quantization stage adds sd[n] to xd[n].

### Claim 2 (depends on 1)

The device of claim 1, wherein each quantization stage discards a predetermined number of least significant bits to implement the quantization.

### Claim 3 (depends on 1)

The device of claim 1, wherein each quantization stage simultaneously divides its input by 2b and quantizes the result by b bits every sample period

### Claim 4 (depends on 3)

The device of claim 3, wherein each quantization stage simultaneously halves its input and quantizes the result by one bit every sample period.

### Claim 5 (depends on 1)

The device of claim 1, wherein numbers within the successive requantizer device are integers with a two's-compliment binary number representation at each time n, and at each quantization stage sd[n] is chosen such that xd[n]+sd[n] does not exceed the range of a (K−d)-bit two's complement integer, and the parity of sd[n] is the same as that of xd[n], where K is determined by the number of quantization stages, the number of bits quantized per stage, and the logic which generates sd[n].

### Claim 6 (depends on 1)

The device of claim 1, wherein that the running sum of each sd[n] sequence, i.e.,
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### Claim 7 (depends on 6)

The device of claim 6, wherein td[n] is a discrete-valued Markov random sequence conditioned on the parity of xd[n].

### Claim 8 (depends on 6)

The device of claim 6, wherein td[n] is a random process whose autocorrelation function converges to a constant as its time spread increases.

### Claim 9 (depends on 6)

The device of claim 6, wherein each quantization stage calculates sd[n] as a function the running sum of td[n] in addition to td[n], an independent random sequence, and the parity of xd[n].

### Claim 10 (depends on 6)

The device of claim 6, wherein each quantization stage calculates sd[n] as a function of the previous value of td[n], the parity of the current value of xd[n], and the current value of an independent random sequence.

### Claim 11 (depends on 1)

The device of claim 1, wherein each quantization stage implements
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can be used, where pd[n] is an independent random sequence that takes on the values 1 and −1 with equal probability.

### Claim 12 (depends on 1)

The device of claim 1, wherein that the running sums of each td,i[n] sequence, i.e.,
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are bounded for all n, and each td,i[n] has a smooth power spectral density that increases monotonically with frequency.

### Claim 13 (depends on 1)

A fractional-N PLL device, comprising:
a phase lock loop generating an output frequency from a voltage controlled oscillator based upon a low frequency reference voltage; and
a successive requantizer according to claim 1 for providing a sequence of integers to control a divider in the phase locked loop to settle to a desired fractional value.

### Claim 14 (depends on 12)

The fractional-N PLL device of claim 12, further comprising an adaptive phase noise cancellation path.

### Claim 15

A successive requantizer device comprising:
a plurality of quantization stages that each accept an input sequence and quantize the input sequence by a predetermined number of bits; wherein
each quantization stage adds a quantization sequence to the quantization stage's input sequence and the quantization sequence is a discrete-valued Markov random sequence conditioned on the parity of the input sequence.

### Claim 16

A successive requantizer device comprising:
a plurality of quantization stages that each accept an input sequence and quantize the input sequence by a predetermined number of bits; wherein
each quantization stage adds a quantization sequence to the quantization stage's input sequence and the quantization sequence is random process whose autocorrelation function converges to a constant as its time spread increases.