# US 2010/0166019 A1 · Subscriber line interface circuitry with integrated serial interfaces

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- Number: US 2010/0166019 A1
- Document ID: US20100166019A1
- Status: Published application
- Kind: A1
- Application number: 12/347,987
- Filed: 2008-12-31
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Inventors: Xun Yang; Jeffrey A. Whaley; Joel W. Page; Gregory James Fyke
- Web page: https://patentgrep.com/patent/US20100166019A1

## CPC

- H04J 3/1694: {Allocation of channels in TDM/TDMA networks, e.g. distributed multiplexers (Passive Optical Networks H04Q11/0062)}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Methods and apparatus for communicating include communicating frames of data having a first timeslot allocation of s timeslots serially from a first device to a second device using a first unidirectional data line at a frequency f1. An edge of each frame as a detected edge. A clock signal having a frequency f2 is generated in response to the detected edges, wherein f 2 f 1 ≈ n · s , wherein n>1, wherein the clock signal is maintained substantially synchronous to the detected edges. Frames of data having a second timeslot allocation of s timeslots are communicated serially from the second device to the first device using a second unidirectional data line at the frequency f1 as derived from f2.

## Claims

### Claim 1

A method of communicating comprising:
a) communicating frames of data having a first timeslot allocation of s timeslots serially from a first device to a second device using a first unidirectional data line at a frequency f1;
b) detecting an edge of each frame as a detected edge;
c) generating a clock signal having a frequency f2 in response to the detected edges, wherein
f
2
f
1
≈
n
·
s
,
wherein n>1, wherein the clock signal is maintained substantially synchronous to the detected edges; and
c) communicating frames of data having a second timeslot allocation of s timeslots serially from the second device to the first device using a second unidirectional data line at the frequency f1 as derived from f2.

### Claim 2 (depends on 1)

The method of claim 1 wherein the second device is a subscriber line interface circuit.

### Claim 3 (depends on 1)

The method of claim 1 wherein the first device is a gateway for an optical network.

### Claim 4 (depends on 1)

The method of claim 1 wherein the first timeslot allocation includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the first timeslot allocation includes at least one CS value and at least one SDI value from an SPI interface of the first device, wherein f1 is an integer multiple of a PCLK associated with a PCM interface of the first device.

### Claim 5 (depends on 4)

The method of claim 4 wherein the first timeslot allocation includes an SDI_V value associated with each SDI value to qualify the validity of the associated SDI values.

### Claim 6 (depends on 1)

The method of claim 1 wherein the second timeslot allocation includes a DTX value from a PCM interface of the second device, wherein the second timeslot allocation includes at least one SDO value from an SPI interface of the second device.

### Claim 7

A communication apparatus, comprising:
a first device;
a second device, wherein the first device communicates frames having a first timeslot allocation of s timeslots serially at a frequency f1 on a first unidirectional data line to the second device, wherein the second device detects an edge of each frame having the first timeslot allocation, wherein the second device generates a clock signal having a frequency f2 in response to the detected edges, wherein
f
2
f
1
≈
n
·
s
,
wherein n>1, wherein the second device communicates frames of data having a second timeslot allocation of s timeslots serially from the second device to the first device using a second unidirectional data line at the frequency f1 as derived from f2.

### Claim 8 (depends on 7)

The apparatus of claim 7 wherein sampling of a first of the plurality of timeslots is selected to occur at a pre-determined one of n clock cycles associated with that timeslot.

### Claim 9 (depends on 7)

The apparatus of claim 7 wherein the second device is a subscriber line interface circuit.

### Claim 10 (depends on 7)

The apparatus of claim 7 wherein the first device is an optical network gateway.

### Claim 11 (depends on 7)

The apparatus of claim 7 wherein the first timeslot allocation includes an FSYNC and a DRX value from a PCM interface of the first device, wherein the timeslot allocation includes at least one CS value and at least one SDI value from an SPI interface of the first device, wherein f1 is a multiple of a PCLK associated with a PCM interface of the first device.

### Claim 12 (depends on 7)

The method of claim 7 wherein the second timeslot allocation includes a DTX value from a PCM interface of the second device, wherein the second timeslot allocation includes at least one SDO value from an SPI interface of the second device.