# US 2010/0166016 A1 · Packet header structure

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- Number: US 2010/0166016 A1
- Document ID: US20100166016A1
- Status: Published application
- Kind: A1
- Application number: 12/595,105
- Filed: 2008-04-14
- Published: 2010-07-01
- Earliest claimed: 2007-04-17
- Assignees: Koninklijke Philips Electronics N.V.
- Inventors: Jeremy Moss; Adrian W. Payne
- Web page: https://patentgrep.com/patent/US20100166016A1

## CPC

- H04L 7/041: {using special codes as synchronising signal}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The present invention relates to a data packet header comprising a first bit field consisting of a first sequence of bits with identical values and a second bit field consisting of a second sequence of bits, the second sequence of bits being subject to a run-length restriction, and located immediately after the first sequence of bits in the order of transmission. The number of bits in the first sequence is equal to or exceeding the run-length restriction and the bits of the second sequence have opposite identical values to the value of the first bit of the second sequence of bits. The invention equally relates to a correlator for detecting a data stream and arranged to determine a correct clock phase for the data stream.

## Claims

### Claim 1

A method of generating a data packet header, comprising:
generating a first bit field having a first sequence of bits with identical values;
placing a second bit field having a second sequence of bits immediately after the first sequence of bits in the order of transmission, the second sequence being subject to a run-length restriction,
wherein the bits of the first sequence are defined as having opposite identical values to the first bit of the second sequence of bits,
the number of bits of the first sequence is defined as being equal or exceeding the maximum run-length restriction, and
all bits in the first and second bit fields serve as device address bits.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The method according to claim 1, wherein all bits in the first and second bit fields serve for clock extraction and word alignment.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the first bit field activates a correlator of a system capable of receiving the packet header once a valid first bit field has been received, the first bit field thereby serving as a wakeup field for the system.

### Claim 5

(canceled)

### Claim 6

A transceiver of a communication system for generating a data packet header, said transceiver comprising:
means for generating a first bit field having a first sequence of bits with identical values;
means for placing a second bit field having a second sequence of bits immediately after the first sequence of bits in the order of transmission, the second sequence being subject to a run-length restriction, said transceiver being arranged such that the bits of the first sequence are defined as having opposite identical values to the first bit of the second sequence of bits, wherein the number of bits of the first sequence is defined as being equal or exceeding the maximum run-length restriction, and all bits in the first and second bit fields serve as device address bits.

### Claim at position 7

7-14. (canceled)

### Claim 15

A computer readable storage medium having stored thereon a data packet header comprising a first bit field having a first sequence of bits with identical values and a second bit field having a second sequence of bits, the second sequence of bits being subject to a run-length restriction, and being located immediately after the first sequence of bits in the order of transmission, the number of bits in the first sequence being equal to or exceeding the run-length restriction, the bits of the first sequence having opposite identical values to the first bit of the second sequence of bits, and all bits in the first and second bit fields serving as device address bits.