# US 2010/0165778 A1 · Word Line Driver Circuit with Reduced Leakage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0165778 A1 - Document ID: US20100165778A1 - Status: Published application - Kind: A1 - Application number: 12/295,745 - Filed: 2007-08-28 - Published: 2010-07-01 - Earliest claimed: 2007-08-28 - Assignees: Agere Systems Inc. - Inventors: Dennis E. Dudeck; Donald Albert Evans; Hai Quang Pham; Wayne E. Werner; Ronald James Wozniak - Web page: https://patentgrep.com/patent/US20100165778A1 ## CPC - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit. ## Claims ### Claim 1 A word line driver circuit for use in a memory array including a plurality of memory cells and a plurality of word lines coupled to the memory cells for selectively accessing the memory cells, the word line driver circuit comprising: a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit; and a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal, the switching circuit being operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal; wherein between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit. ### Claim 2 (depends on 1) The word line driver circuit of claim 1, further comprising a control circuit operative to generate the at least one control signal as a function of a second set of address signals received by the word line driver circuit. ### Claim 3 (depends on 2) The word line driver circuit of claim 2, wherein the control circuit is operative to generate a plurality of control signals, the control circuit comprising a plurality of logical AND function elements, each of the AND function elements being operative to receive at least a subset of the second set of address signals, at least one address signal in the subset of the second set of address signals being unique to each of the respective AND function elements, each of the AND function elements generating a respective one of the plurality of control signals so as to selectively activate a corresponding one of the word lines. ### Claim 4 (depends on 2) The driver circuit of claim 2, wherein the control circuit is operative to generate a plurality of control signals, the control circuit comprising a plurality of three-input logical NAND gates, a first input of each of the NAND gates receiving a first one of the address signals in the second set of address signals, a second input of each of the NAND gates receiving a second one of the address signals in the second set of address signals, and a third input of each of the NAND gates receiving a unique one of the address signals in the second set of address signals, the NAND gates generating respective ones of the plurality of control signals at outputs thereof as a function of the respective inputs to the NAND gates. ### Claim 5 (depends on 1) The word line driver circuit of claim 1, wherein the control circuit is operative to generate a plurality of control signals, wherein the switching circuit comprises a plurality of switch elements, each of the switch elements connected to a corresponding one of the word lines at a first node and receiving the word line signal at a second node, each of the switch elements being selectively activated by a corresponding one of the control signals. ### Claim 6 (depends on 5) The word line driver circuit of claim 5, wherein at least one of the switch elements comprises a transmission gate. ### Claim 7 (depends on 5) The word line driver circuit of claim 5, wherein at least one of the switch elements comprises a complementary pass gate. ### Claim 8 (depends on 7) The word line driver circuit of claim 7, wherein the complementary pass gate comprises: a PMOS device including a first source/drain connected to the input node of the switching circuit, a second source/drain connected to a corresponding one of the output nodes of the switching circuit, and a gate for receiving a corresponding one of the control signals; and an NMOS device including a first source/drain connected to the first source/drain of the PMOS device, a second source/drain connected to the second source/drain of the PMOS device, and a gate for receiving a logical complement of the corresponding one of the control signals. ### Claim 9 (depends on 1) The word line driver circuit of claim 1, wherein the switching circuit further comprises a plurality of transistor devices, each of the transistor devices connected to a corresponding one of the word lines and being operative to selectively connect the respective word lines to a prescribed voltage level when the word lines are not being accessed. ### Claim 10 (depends on 9) The word line driver circuit of claim 9, wherein at least one of the transistor devices is an NMOS device having a first source/drain connected to a corresponding one of the word lines, a second source/drain connecting to a voltage source having the prescribed voltage level, and a gate for receiving a corresponding one of a plurality of control signals. ### Claim 11 (depends on 9) The word line driver circuit of claim 9, wherein the prescribed voltage level is substantially equal to zero volts. ### Claim 12 (depends on 1) The word line driver circuit of claim 1, wherein the driver comprises: a decoder circuit operative to receive the first set of address signals and to generate a decoded address signal as a function thereof; and an inverter having an input connected to the decoder circuit and an output for generating the word line signal as a function of the decoded address signal. ### Claim 13 (depends on 12) The word line driver circuit of claim 12, wherein the decoder circuit comprises a logical AND function element, the AND function element receiving at least a portion of the first set of address signals and generating the decoded address signal as a function thereof for selecting a given one of the word lines. ### Claim 14 (depends on 12) The word line driver circuit of claim 12, wherein the decoder circuit comprises a two-input logical NAND gate, a first input of the NAND gate receiving a first one of the address signals in the first set of address signals, a second input of the NAND gate receiving a second one of the address signals in the first set of address signals, and an output of the NAND gate generating the decoded address signal as a function of the first and second one of the address signals in the first set of address signals. ### Claim 15 (depends on 1) The word line driver circuit of claim 1, wherein at least a portion of the signals in at least one of the first and second sets of address signals comprises pre-decoded address signals. ### Claim 16 (depends on 1) The word line driver circuit of claim 1, wherein at least one of the address signals in first set of address signals is the same as one of the address signals in the second set of address signals. ### Claim 17 (depends on 1) The word line driver circuit of claim 1, wherein: the switching circuit comprises: a plurality of transmission gates, each of the transmission gates, at a first node thereof, connected to a corresponding one of the word lines; and a plurality of switch devices, each of the switch devices being connected to the first node of a corresponding one of the transmission gates and being operative to selectively connect a corresponding one of the word lines to a prescribed voltage level when the transmission gate connected thereto is disabled; the output of the driver is connected to a second node of each of the plurality of transmission gates and is adapted to receive the first set of address signals for activating a selected one of the word lines via a corresponding one of the transmission gates; the word line driver circuit further comprising a control circuit operative to generate a plurality of control signals, each of the control signals selectively enabling a respective one of the transmission gates, the control circuit being operative to receive a second set of address signals and to generate the control signals as a function thereof. ### Claim 18 (depends on 1) The word line driver circuit of claim 1, further comprising a control circuit operative to generate the plurality of control signals as a function of a second set of address signals presented to the word line driver circuit. ### Claim 19 (depends on 1) An integrated circuit comprising at least one word line driver circuit according to claim 1. ### Claim 20 A system having reduced leakage current, comprising: a memory array including a plurality of memory cells and a plurality of word lines coupled to the memory cells for selectively accessing the memory cells; and at least one word line driver circuit coupled to the memory array, the word line driver circuit comprising: a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit; and a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal, the switching circuit being operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal; wherein between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.