# US 2010/0165776 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0165776 A1 - Document ID: US20100165776A1 - Status: Published application - Kind: A1 - Application number: 12/280,074 - Filed: 2007-02-22 - Published: 2010-07-01 - Earliest claimed: 2006-02-24 - Assignees: Renesas Technology Corp. - Inventors: Akira Tada - Web page: https://patentgrep.com/patent/US20100165776A1 ## CPC - G06F 1/32: Means for saving power - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - H04W 52/0261: {managing power supply demand, e.g. depending on battery level} - Y02D 30/70: in wireless communication networks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A semiconductor device capable of reducing power consumption is provided. When a power to an internal circuit is interrupted, e.g., in a standby mode, a switch is turned off, and a pseudo-ground line is charged with a leak current of the internal circuit to raise a potential thereof. After the switch is turned off, a switch connected to a charge supply unit is turned on while the potential is rising, so that the charge supply unit is electrically coupled to the pseudo-ground line. Thereby, charges accumulated in the charge supply unit are discharged to the pseudo-ground line. The switch is turned off to decouple electrically the charge supply unit from the pseudo-ground line. Thereby, when the power supply is interrupted, a part of the charges for raising the potential of the pseudo-ground line is supplemented with the charges of the charge supply unit. ## Claims ### Claim 1 A semiconductor device comprising: a first voltage interconnection supplying a first voltage; a second voltage interconnection supplying a second voltage; a first voltage supply interconnection arranged between said first voltage interconnection and said second voltage interconnection; a first internal circuit connected between said second voltage interconnection and said first voltage supply interconnection, and forming a current path between said second voltage interconnection and said first voltage supply interconnection in response to an input signal; a first switch connected between said first voltage interconnection and said first voltage supply interconnection, and being turned on in response to an input first control signal; a charge supply unit charging said first voltage supply interconnection; and a second switch connected between said first voltage supply interconnection and said charge supply unit, and being turned on in response to an input second control signal. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a third voltage interconnection supplying a third voltage; a second voltage supply interconnection arranged between said first voltage interconnection and said third voltage interconnection; a second internal circuit connected between said third voltage interconnection and said second voltage supply interconnection, and forming a current path between said third voltage interconnection and said second voltage supply interconnection in response to an input signal; and a third switch connected between said first voltage interconnection and said second voltage supply interconnection, and being turned on in response to an input third control signal, wherein said charge supply unit corresponds to said second voltage supply interconnection. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein said first and second switches are electrically coupled to said first voltage supply interconnection via an internal node, and said semiconductor device further comprises a third switch connected between said internal node and said first voltage supply interconnection, and being turned on in response to an input third control signal. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising: a third voltage interconnection supplying a third voltage; a second voltage supply interconnection arranged between said first and third voltage interconnections; and a second internal circuit connected between said first voltage interconnection and said second voltage supply interconnection, and forming a current path between said first voltage interconnection and said second voltage supply interconnection in response to an input signal, wherein said charge supply unit corresponds to said second voltage supply interconnection. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein said charge supply unit includes a capacitor accumulating charges. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein said charge supply unit includes a power supply unit for charging said first voltage supply interconnection. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein said power supply unit includes a generator element generating an electric power by converting physical energy other than electric energy into electric energy. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein at least one of said corresponding switches receives input of the plurality of corresponding control signals, and electrically couples one of corresponding ends to the other corresponding end based on a combination of said plurality of corresponding control signals. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein said first internal circuit and said first voltage supply interconnection are formed in a first chip, and said charge supply unit is formed in a second chip. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein said first input circuit, said first voltage supply interconnection and said first switch are formed in a first chip, and at least one of said charge supply unit and said second switch is formed in a second chip. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein said first internal circuit corresponds to a memory array having a plurality of memory cells. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein each of said memory cells includes a flip-flop circuit for setting said first and second storage nodes to different potential levels, respectively, according to data to be stored; said flip-flop circuit includes: a first transistor connected between said second voltage and said first storage node, and having a gate electrically coupled to said second storage node, a second transistor connected between said voltage supply interconnection and said first storage node, and having a gate electrically coupled to said second storage node, a third transistor connected between said second voltage and said second storage node, and having a gate electrically coupled to said first storage node, and a fourth transistor connected between said voltage supply interconnection and said second storage node, and having a gate electrically coupled to said first storage node; said first switch is turned off in response to said first control signal in a data write operation; and said first voltage supply interconnection is set to a potential intermediate between said first and second voltages. ### Claim 13 (depends on 2) The semiconductor device according to claim 2, wherein at least one of said first and second internal circuits corresponds to at least one of a plurality of memory blocks each having a plurality of memory cells. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, further comprising: a third voltage interconnection supplying a third voltage; said first switch includes: a first switch unit connected between said first voltage supply interconnection and said first voltage interconnection, and a first logic circuit controlling said first switch unit in response to a command signal; and said first logic circuit includes: a second switch unit connected between said third voltage interconnection and a control terminal of said first switch unit, and electrically coupling said third voltage interconnection to the control terminal of said first switch unit in response to a command signal setting said first switch unit to a conductive state, and a third switch unit connected between said first voltage supply interconnection and the control terminal of said first switch unit, and electrically coupling said first voltage supply interconnection to the control terminal of said first switch unit in response to a command signal implementing an nonconductive state reducing a quantity of a current flowing to said first switch unit as compared with the conductive state. ### Claim 15 A semiconductor device comprising: a first voltage interconnection supplying a first voltage; a second voltage interconnection supplying a second voltage; one or a plurality of first voltage supply interconnection(s) connected between said first and second voltage interconnections; one or a plurality of first internal circuit(s) connected between said second voltage interconnection and said one or said plurality of first voltage supply interconnection(s), and forming a current path(s) between said second voltage interconnection and said one or said plurality of first voltage supply interconnection(s) in response to an input signal; one or a plurality of first switches connected between said first voltage interconnection and said one or said plurality of first voltage supply interconnection(s), and being turned on in response to an input first control signal; one or a plurality of charge supply unit(s) charging said one or said plurality of first voltage supply interconnection(s); and a plurality of second switches connected between said one or said plurality of voltage supply interconnection(s) and said one or said plurality of charge supply unit(s), and being turned on in response to an input second control signal, said second control signal corresponding to a plurality of command signals being input corresponding to said plurality of second switches, respectively; and a first control circuit producing said plurality of command signals to turn on at least a part of said plurality of second switches according to timing different from that of the other second switch(es). ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein said one or said plurality of first switches and said plurality of second switches are electrically coupled to said one or said plurality of first voltage supply interconnection(s) via an internal node, and said semiconductor device further comprises a third switch connected between said internal node and said one or said plurality of first voltage supply interconnections, and being turned on in response to an input third control signal.