# US 2010/0165759 A1 · Semiconductor Memory Device and Operation Method Thereof

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- Number: US 2010/0165759 A1
- Document ID: US20100165759A1
- Status: Published application
- Kind: A1
- Application number: 12/489,534
- Filed: 2009-06-23
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: Hynix Semiconductor Inc.
- Inventors: Byeong-Chan Choi
- Web page: https://patentgrep.com/patent/US20100165759A1

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1066: {Output synchronization}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a strobe signal generator for receiving a write command and generating a write strobe signal that defines an activation period variably according to an operation frequency, and a data transfer unit for transferring data from an external device to an internal data line in response to the write strobe signal.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a strobe signal generator configured to receive a write command and to generate a write strobe signal that defines an activation period variably based on an operation frequency; and
a data transfer unit configured to transfer data from an external device to an internal data line in response to the write strobe signal.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, further comprising: a pulse delay unit configured to delay a write pulse signal until a predetermined time point where the write pulse signal is generated in response to the write command.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the pulse delay unit includes:
a write pulse generator configured to generate the write pulse signal having a predetermined pulse width in response to the write command; and
a delay unit configured to delay the write pulse signal by a predetermined time interval.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, further comprising: a data aligner configured to align the data from an external device in parallel and inputting the aligned data to the data transfer unit.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein the data aligner includes a plurality of latches that latch the data from an external device in response to a data strobe signal.

### Claim 6 (depends on 2)

The semiconductor memory device of claim 2, wherein the write pulse signal has CAS latency information, additive latency information, and burst length information.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, wherein the strobe signal generator includes:
a control signal generator configured to generate a control signal that controls an activation period of the write strobe signal in response to the operation frequency; and
a strobe signal output unit configured to output the write strobe signal in response to the write command and the control signal.

### Claim 8 (depends on 7)

The semiconductor memory device of claim 7, wherein the strobe signal is activated in response to the write command and inactivated in response to the control signal.

### Claim 9 (depends on 7)

The semiconductor memory device of claim 7, wherein the control signal controls a delay amount corresponding to an inactivation time of the write strobe signal.

### Claim 10 (depends on 7)

The semiconductor memory device of claim 7, wherein the strobe signal output unit includes:
a first driver configured to drive in response to an activation edge of the write pulse signal; and
a second driver configured to drive in response to an inactivation edge of the write pulse signal and controlling a load value of a driving path in response to the control signal.

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, wherein the operation frequency corresponds to CAS latency.

### Claim 12

A method of driving a semiconductor memory device, comprising:
activating a write strobe signal in response to a write command;
sustaining activation of the write strobe signal during a period corresponding to an operation frequency; and
transferring data from an external device to an internal data line in response to the write strobe signal.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
aligning the data from an external device in parallel;
generating a write pulse signal having a predetermined pulse width in response to the write command; and
delaying the write pulse signal by a predetermined time interval.

### Claim 14 (depends on 13)

The method of claim 13, wherein the aligning of the data includes sequentially latching the data from an external device in response to a data strobe signal.

### Claim 15 (depends on 13)

The method of claim 13, wherein the write pulse signal includes CAS latency information, additive latency information, and burst length information.

### Claim 16 (depends on 12)

The method of claim 12, wherein the sustaining activation of the write strobe signal includes:
generating a control signal for controlling an activation period of the write strobe signal in response to the operation frequency; and
outputting the write strobe signal in response to the write command and the control signal.

### Claim 17 (depends on 16)

The method of claim 16, wherein the write strobe signal is activated in response to the write command and inactivated in response to the control signal.

### Claim 18 (depends on 16)

The method of claim 16, wherein the control signal controls a delay amount corresponding to an inactivation time of the write strobe signal.

### Claim 19 (depends on 16)

The method of claim 16, wherein the outputting of the write strobe signal includes:
driving corresponding to an activation edge of the write pulse signal;
controlling a load value of a driving path in response to the control signal; and
reflecting a load value of the driving path and driving corresponding to an inactivation edge of the write pulse signal.

### Claim 20 (depends on 12)

The method of claim 12, wherein the operation frequency corresponds to CAS latency.