# US 2010/0165758 A1 · Semiconductor memory device and method for operating the same

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- Number: US 2010/0165758 A1
- Document ID: US20100165758A1
- Status: Published application
- Kind: A1
- Application number: 12/346,074
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Assignees: Hynix Semiconductor Inc.
- Inventors: Jung-Hoon PARK; Young-Ho JUNG
- Web page: https://patentgrep.com/patent/US20100165758A1

## CPC

- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The semiconductor memory device includes a data input/output unit configured to input data synchronously with a data clock and to output the data to a memory cell in response to an output strobe signal; and an output strobe signal generation unit configured to output the output strobe signal, wherein the output strobe signal is synchronized with a system clock in response to a write command regardless of whether the semiconductor memory device is in a write training mode.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a data input/output unit configured to input data synchronously with a data clock and to output the data to a memory cell in response to an output strobe signal; and
an output strobe signal generation unit configured to output the output strobe signal, wherein the output strobe signal is synchronized with a system clock in response to a write command.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the output strobe signal generation unit includes:
a core control unit configured to output a core enable signal synchronized with the system clock in response to the write command, the memory cell being enabled by the core enable signal; and
a data output control unit configured to delay the core enable signal by a predetermined time and output the delayed core enable signal as the output strobe signal in order to secure a time when the data is stored in the data input/output unit.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein the core control unit is configured to delay and output the core enable signal in response to write latency.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2, further comprising:
a core enable signal control unit configured to delay the core enable signal by a predetermined amount and to output the delayed core enable signal to the memory cell.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein the core enable signal control unit is configured to disable the core enable signal in a write training mode and to output the core enable signal to the memory cell.

### Claim 6 (depends on 4)

The semiconductor memory device of claim 4, wherein the core enable signal control unit includes:
an AND gate configured to receive a write training signal for informing of the write training mode and the core enable signal; and
a delay device configured to delay an output signal of the AND gate by the predetermined time in order to output the delayed output signal.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1, wherein a frequency of the data clock is two times higher than a frequency of the system clock.

### Claim 8

A semiconductor memory device, comprising:
a data input/output unit configured to receive and store data in response to an input strobe signal and to output the stored data to a memory cell in response to an output strobe signal;
a clock dividing unit configured to output multi-phase clocks by dividing a data clock;
a data input control unit configured to output the input strobe signal, wherein the input strobe signal is synchronized with the multi-phase clocks, in response to a write enable signal; and
an output strobe signal generation unit configured to output the output strobe signal, wherein the input strobe signal is synchronized with a system clock, in response to the write enable signal.

### Claim 9 (depends on 8)

The semiconductor memory device of claim 8, wherein the output strobe signal generation unit includes:
a core control unit configured to output a core enable signal synchronized with the system clock in response to the write enable signal, the memory cell being enabled by the core enable signal; and
a data output control unit configured to delay the core enable signal by a predetermined time and output the delayed core enable signal as the output strobe signal in order to secure a time when the data is stored in the data input/output unit.

### Claim 10 (depends on 9)

The semiconductor memory device of claim 9, wherein each of the core control unit and the data input control unit is configured to delay and output the core enable signal and the input strobe signal by being reflected by write latency.

### Claim 11 (depends on 10)

The semiconductor memory device of claim 10, wherein each of the core control unit and the data input control unit includes:
a plurality of latency shifters, each of said plurality of latency shifters being connected in series and configured to delay the write enable signal in response to the write latency in order to individually output the core enable signal and the input strobe signal; and
a pulse width adjusting unit configured to adjust an enable period width of each of the core enable signal and the input strobe signal.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein each of the latency shifters includes:
a write enable signal input unit configured to transmit the write enable signal in response to the write latency; and
a flip-flop configured to receive and shift a signal transmitted by the write enable signal input unit.

### Claim 13 (depends on 8)

The semiconductor memory device of claim 8, wherein the data input/output unit includes:
a data aligning unit configured to align the data inputted in series in parallel in response to the multi-phase clocks; and
at least one resistor configured to receive and store the parallel data in response to the input strobe signal and to output the stored parallel data in response to the output strobe signal.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13, wherein the at least one resistor includes:
a first pass gate turned on or off in response to the input strobe signal;
a second pass gate turned on or off in response to the output strobe signal; and
a plurality of latch units configured to latch output signals of the first and the second pass gates.

### Claim 15 (depends on 8)

The semiconductor memory device of claim 8, wherein the clock dividing unit is configured to divide the data clock into two and to output the multi-phase clocks with phase differences from adjacent clocks by 90°.

### Claim 16 (depends on 9)

The semiconductor memory device of claim 9, further comprising:
a core enable signal control unit configured to delay the core enable signal by the predetermined time and to output the delayed core enable signal to the memory.

### Claim 17 (depends on 16)

The semiconductor memory device of claim 16, wherein the core enable signal control unit is configured to disable the core enable signal in response to a write training signal for informing of the write training mode and to output the core enable signal to the memory cell.

### Claim 18 (depends on 16)

The semiconductor memory device of claim 16, wherein the core enable signal control unit includes:
an AND gate configured to receive the write training signal for informing of the write training mode and the core enable signal; and
a delay device configured to delay an output signal of the AND gate by a predetermined time in order to output the delayed output signal.

### Claim 19 (depends on 8)

The semiconductor memory device of claim 8, further comprising:
a command decoder unit configured to output the write enable signal and the write training signal for informing of the write training mode in response to a write command inputted from an outside.

### Claim 20 (depends on 8)

The semiconductor memory device of claim 8, wherein a frequency of the data clock is two times higher than a frequency of the system clock.

### Claim 21

A method for operating a semiconductor memory device, comprising:
generating a write enable signal and a write training signal enabled in a write training mode in response to a write command;
generating a core enable signal, wherein the core enable signal is synchronized with a system clock in response to the write enable signal;
generating an output strobe signal by delaying the core enable signal by a predetermined time;
disabling the core enable signal based on the write training mode in order to transmit the disabled core enable signal to a memory cell, wherein the memory cell is enabled by the enabled core enable signal;
generating multi-phase clocks by dividing a data clock;
generating an input strobe signal synchronized with the multi-phase clocks in response to the write enable signal; and
receiving and storing data in response to the input strobe signal and outputting the stored data to the memory cell in response to the output strobe signal.

### Claim 22 (depends on 21)

The method of claim 21, wherein the core enable signal is delayed by the predetermined time in order to secure a storage time of the inputted data in response to the input strobe signal in generating the output strobe signal.

### Claim 23 (depends on 22)

The method of claim 22, wherein the core enable signal is delayed by the predetermined time in disabling the core enable signal in order to output the disabled core enable signal to the memory cell.

### Claim 24 (depends on 21)

The method of claim 21, wherein each of the core enable signal and the input strobe signal is delayed and generated by reflecting write latency in generating the core enable signal and generating the input strobe signal respectively.