# US 2010/0165709 A1 · Robust sram memory cell capacitor plate voltage generator

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- Number: US 2010/0165709 A1
- Document ID: US20100165709A1
- Status: Published application
- Kind: A1
- Application number: 12/645,039
- Filed: 2009-12-22
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: STMicroelectronics S.r.l.; Medtronic, Inc.
- Inventors: Kevin K. Walsh; Paul F. Gerrish; Larry E. Tyler; Mark A. Lysinger; David C. McClure; Francois Jacquet
- Web page: https://patentgrep.com/patent/US20100165709A1

## CPC

- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 11/417: for memory cells of the field-effect type
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

## Claims

### Claim 1

A device comprising:
a memory cell having:
a first capacitor; and
a second capacitor in series with the first capacitor, the first and second capacitors being coupled together at a common node;
a first transistor connected in the off condition; and
a second transistor connected in the off condition, the second transistor coupled in series with the first transistor, the first and second transistors connected to always be off and to supply to the common node a capacitor supply voltage, the first transistor configured to generate the capacitor supply voltage by a leakage current of the first transistor in the off condition.

### Claim 2 (depends on 1)

The device of claim 1 wherein the memory cell is an SRAM memory cell having a first inverter, the first and second capacitors being coupled in series between an input and an output of the first inverter.

### Claim 3 (depends on 1)

The device of claim 1 wherein the capacitor supply voltage is approximately midway between a voltage of a first supply rail and a voltage of a second supply rail.

### Claim 4 (depends on 3)

The device of claim 3 wherein the first and the second transistors are in series with each other between the first supply rail and the second supply rail.

### Claim 5 (depends on 3)

The device of claim 3 wherein the first and the second transistors are in series between a third voltage supply and a fourth voltage supply.

### Claim 6 (depends on 5)

The device of claim 5 wherein a voltage difference between the third and fourth supplies is smaller than a voltage difference between the first and second supplies.

### Claim 7

A memory comprising:
a plurality of SRAM memory cells, each SRAM memory cell respectively comprising:
an inverter;
a first capacitor; and
a second capacitor in series with the first capacitor and sharing a common node with the first capacitor; and
a voltage generator having a first transistor and configured to supply to the respective common nodes of the respective memory cells a capacitor supply voltage, the capacitor supply voltage being approximately midway between a high voltage supply level of the memory and a low voltage supply level of the memory, the first transistor being configured to generate the capacitor supply voltage by a leakage current of the first transistor.

### Claim 8 (depends on 7)

The memory of claim 7 wherein the leakage current of the first transistor compensates for a leakage of at least one of the first or second capacitors.

### Claim 9 (depends on 7)

The memory of claim 7 wherein the voltage generator comprises a second transistor in series with the first transistor, the first and the second transistors being off.

### Claim 10 (depends on 9)

The memory of claim 9 wherein the first transistor is coupled to the high voltage supply level and the second transistor is coupled to the low voltage supply level.

### Claim 11

An internal defibrillator comprising:
a battery;
a memory coupled to the battery, the memory having;
a plurality of memory cells, each memory cell respectively including;
a first capacitor; and
a second capacitor in series with the first capacitor, the first and second capacitors being coupled together at a common node;
a voltage generator including a transistor and configured to generate a capacitor supply voltage by a leakage current of the transistor, the voltage generator configured to supply the capacitor supply voltage to the respective common nodes of the respective memory cells; and
electrodes coupled to the battery and the memory.

### Claim 12

A device comprising:
a memory cell having an inverter, the inverter having an input and an output;
a first capacitor having a first node and a second node, the first node of the first capacitor being coupled to the input of the inverter;
a second capacitor having a first node and a second node, the first node being coupled to the output of the inverter and the second node of the second capacitor being coupled to the second node of the first capacitor, the first node of the second capacitor being coupled to the output of the inverter; and
a voltage generator having a first transistor with a gate held at the off voltage level and coupled to supply to the second nodes of the first and second capacitors a capacitor supply voltage generated from a leakage current of the first transistor.

### Claim 13 (depends on 12)

The device of claim 12 wherein the voltage generator comprises a second transistor in series with the first transistor, the first and second transistors being coupled at a common node to the second nodes of the first and second capacitors.

### Claim 14 (depends on 13)

The device of claim 13 wherein the first and second transistors are PMOS transistors, a drain of the first transistor being coupled at the common node to a source of the second transistor.

### Claim 15 (depends on 14)

The device of claim 14 wherein a source of the first transistor is coupled to a high voltage supply of the device, a drain of the second transistor being coupled to a low voltage supply of the device.

### Claim 16 (depends on 15)

The device of claim 15 wherein a gate and a body of the first transistor are coupled to the high voltage supply, a gate and a body of the second transistor being coupled to the common node.

### Claim 17 (depends on 12)

The device of claim 12 wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.