# US 2010/0165708 A1 · Memory controller and decoder

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- Number: US 2010/0165708 A1
- Document ID: US20100165708A1
- Status: Published application
- Kind: A1
- Application number: 12/397,614
- Filed: 2009-03-04
- Published: 2010-07-01
- Earliest claimed: 2008-12-25
- Assignees: Winbond Electronics Corp.
- Inventors: Cheng-Sheng Lee
- Web page: https://patentgrep.com/patent/US20100165708A1

## CPC

- H03K 19/0013: {in field effect transistor circuits}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/10: Decoders
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.

## Claims

### Claim 1

A decoder, comprising:
a first transistor, having a gate and a first terminal coupled to a first control signal and a first voltage respectively;
a second transistor, having a gate and a first terminal coupled to a second control signal and a second terminal of the first transistor respectively;
a third transistor, having a gate, a first terminal, and a second terminal coupled to a third control signal, a second terminal of the second transistor, and a second voltage respectively; and
a fourth transistor, having a gate, a first terminal, and a second terminal coupled to a fourth control signal, the second terminal of the second transistor, and the second voltage respectively,
wherein when the first transistor is turned off and the second transistor is turned off, a voltage of the second control signal is lower than a voltage of the first control signal.

### Claim 2 (depends on 1)

The decoder according to claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are a P-channel metal oxide semiconductor field effect transistor, a P-channel metal oxide semiconductor field effect transistor, an N-channel metal oxide semiconductor field effect transistor, and an N-channel metal oxide semiconductor field effect transistor respectively.

### Claim 3 (depends on 1)

The decoder according to claim 1, further comprising:
a fifth transistor, having a gate, a first terminal, and a second terminal coupled to a fifth control signal, the second terminal of the second transistor, and the second voltage respectively.

### Claim 4 (depends on 3)

The decoder according to claim 3, wherein the fifth transistor is an N-channel metal oxide semiconductor field effect transistor.

### Claim 5 (depends on 1)

The decoder according to claim 1, wherein the second terminal of the second transistor serves as an output terminal of the decoder.

### Claim 6

A memory controller, comprising:
a first inverter, for receiving a first control signal and generating a second control signal accordingly;
a second inverter, having an input terminal coupled to an output terminal of the first inverter, for receiving the second control signal and generating a third control signal accordingly; and
an output unit, coupled to an output terminal of the second inverter, wherein the output unit comprises:
a first transistor, having a gate receiving the third control signal, and a first terminal coupled to a first voltage;
a second transistor, having a gate receiving the third control signal, and a first terminal coupled to a second terminal of the first transistor; and
a third transistor, having a gate, a first terminal, and a second terminal coupled to a fourth control signal, a second terminal of the second transistor, and a second voltage respectively;
wherein when the second transistor is turned off and the third transistor is turned off, a voltage of the fourth control signal is higher than a voltage of the third control signal.

### Claim 7 (depends on 6)

The memory controller according to claim 6, wherein the first transistor, the second transistor, and the third transistor are a P-channel metal oxide semiconductor field effect transistor, an N-channel metal oxide semiconductor field effect transistor, and an N-channel metal oxide semiconductor field effect transistor respectively.

### Claim 8 (depends on 6)

The memory controller according to claim 6, further comprising:
a third inverter, having an input terminal coupled to the output terminal of the first inverter, for receiving the second control signal and outputting a fifth control signal accordingly.