# US 2010/0165707 A1 · Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0165707 A1 - Document ID: US20100165707A1 - Status: Published application - Kind: A1 - Application number: 12/345,125 - Filed: 2008-12-29 - Published: 2010-07-01 - Earliest claimed: 2008-12-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yen-Huei Chen; Jui-Jen Wu - Web page: https://patentgrep.com/patent/US20100165707A1 ## CPC - G11C 11/412: using field-effect transistors only - H10B 10/00: Static random access memory [SRAM] devices - H10B 10/12: {comprising a MOSFET load element} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/6215: {having multiple independently-addressable gate electrodes} - H10D 89/10: Integrated device layouts - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate. ## Claims ### Claim 1 An integrated circuit structure comprising: a static random access memory (SRAM) cell comprising: a first pull-up transistor; and a first pull-down transistor forming a first inverter with the first pull-up transistor, wherein the first pull-down transistor comprises a front gate connected to a gate of the first pull-up transistor, and a back-gate decoupled from the front gate. ### Claim 2 (depends on 1) The integrated circuit structure of claim 1, wherein the SRAM cell further comprises: a second pull-up transistor; and a second pull-down transistor forming a second inverter with the second pull-up transistor, wherein the first inverter and the second inverter are cross-coupled, and wherein the second pull-down transistor comprises a front gate connected to a gate of the second pull-up transistor, and a back-gate coupled to the back-gate of the first pull-down transistor. ### Claim 3 (depends on 2) The integrated circuit structure of claim 2, wherein the back-gate of the first pull-down transistor is directly connected to the back-gate of the second pull-down transistor. ### Claim 4 (depends on 1) The integrated circuit structure of claim 1 further comprising a back-gate controller coupled to the back-gate of the first pull-down transistor, wherein the back-gate controller is configured to apply a first voltage to the back-gate of the first pull-down transistor in a first operation of the SRAM cell, and apply a second voltage different from the first voltage to the back-gate of the first pull-down transistor in a second operation of the SRAM cell. ### Claim 5 (depends on 4) The integrated circuit structure of claim 4, wherein the first operation is a write operation, the second operation is a read operation, and wherein the first voltage is lower than a threshold voltage of the back-gate of the first pull-down transistor, and the second voltage is greater than the threshold voltage. ### Claim 6 (depends on 4) The integrated circuit structure of claim 4, wherein the first operation is a write operation, the second operation is a read operation, and wherein the first voltage is an electrical ground voltage, and the second voltage is substantially equal to a positive power supply voltage VDD of the SRAM cell. ### Claim 7 (depends on 4) The integrated circuit structure of claim 4, wherein the first operation is a write operation, and wherein the first voltage is a negative voltage. ### Claim 8 (depends on 4) The integrated circuit structure of claim 4, wherein the first operation is a sleep mode operation, and wherein the first voltage is lower than a threshold voltage of the back-gate of the first pull-down transistor. ### Claim 9 (depends on 4) The integrated circuit structure of claim 4, wherein the first operation is a sleep mode operation, the second operation is a write operation, and wherein the first voltage is a negative voltage with a voltage level lower than the second voltage. ### Claim 10 (depends on 1) The integrated circuit structure of claim 1, wherein the first pull-down transistor is a FinFET comprising a fin, and wherein the front gate is on a first sidewall of the fin, and the back-gate is on a second sidewall of the fin opposite the first sidewall. ### Claim 11 An integrated circuit structure comprising: a word-line; a first Y-direction select line; a first static random access memory (SRAM) cell coupled to the word-line and comprising: a first inverter comprising: a first pull-up transistor; and a first pull-down transistor coupled to the first pull-up transistor and comprising a first front gate and a first back-gate; and a second inverter cross-coupled to the first inverter and comprising: a second pull-up transistor; and a second pull-down transistor coupled to the second pull-up transistor and comprising a second front gate and a second back-gate, wherein the first back-gate and the second back-gate are connected to the first Y-direction select line. ### Claim 12 (depends on 11) The integrated circuit structure of claim 11, wherein the first pull-down transistor is a FinFET comprising a fin, and wherein the first front gate is on a first sidewall of the fin, and the first back-gate is on a second sidewall of the fin opposite the first sidewall. ### Claim 13 (depends on 11) The integrated circuit structure of claim 11, wherein the first pull-up transistor and the second pull-up transistor are single-gate transistors. ### Claim 14 (depends on 11) The integrated circuit structure of claim 11 further comprising a first pass-gate transistor coupled between the first inverter and a first bit-line, and a second pass-gate transistor coupled between the second inverter and a second bit-line, wherein the first pass-gate transistor and the second pass-gate transistor are single-gate transistors. ### Claim 15 (depends on 11) The integrated circuit structure of claim 11 further comprising a back-gate controller comprising a first output coupled to the first Y-direction select line, wherein the back-gate controller is configured to apply a first voltage to the first Y-direction select line in a first operation of the first SRAM cell, and apply a second voltage different from the first voltage to the first Y-direction select line in a second operation of the SRAM cell. ### Claim 16 (depends on 11) The integrated circuit structure of claim 11 further comprising: a second SRAM cell coupled to the word-line and comprising an additional pull-down transistor, wherein the additional pull-down transistor comprises an additional front gate and an additional back-gate; a second Y-direction select line connected to the additional back-gate; and a back-gate controller comprising a first output coupled to the first Y-direction select line, and a second output coupled to the second Y-direction select line, wherein the back-gate controller is configured to apply a first voltage to the first Y-direction select line in a write operation, and apply a second voltage higher than the first voltage to the second Y-direction select line in the write operation, and wherein the first SRAM cell is a selected cell for the write operation, and the second SRAM cell is an unselected cell for the write operation. ### Claim 17 (depends on 16) The integrated circuit structure of claim 16, wherein the back-gate controller is configured to apply a voltage close to a positive power supply voltage of the first SRAM cell to the first Y-direction select line and the second Y-direction select line in a read operation. ### Claim 18 (depends on 16) The integrated circuit structure of claim 16, wherein the back-gate controller is configured to apply a negative voltage to the first Y-direction select line and the second Y-direction select line is in a sleep mode operation. ### Claim 19 (depends on 11) The integrated circuit structure of claim 11, wherein the first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors. ### Claim 20 An integrated circuit structure comprising: static random access memory (SRAM) cells arranged as an array comprising rows and columns, wherein each of the SRAM cells comprises: a first inverter coupled to a power supply voltage node and comprising: a first pull-up transistor; and a first pull-down transistor coupled to the first pull-up transistor, wherein the first pull-down transistor comprises a first front gate and a first back-gate; and a second inverter cross-coupled to the first inverter, and coupled to the power supply voltage node, the second inverter comprising: a second pull-up transistor; and a second pull-down transistor coupled to the second pull-up transistor, wherein the second pull-down transistor comprises a second front gate and a second back-gate, and wherein the first back-gate and the second back-gate are interconnected; and Y-direction select lines extending in a column direction, wherein each of the Y-direction select lines is coupled to the first back-gate and the second back-gate of all of the SRAM cells in a same column. ### Claim 21 (depends on 20) The integrated circuit structure of claim 20, wherein the first pull-up transistor and the second pull-up transistor are single-gate transistors having gates connected to the front gate of the first pull-down transistor and the front gate of the second pull-down transistor, respectively. ### Claim 22 (depends on 20) The integrated circuit structure of claim 20 further comprising a back-gate controller comprising a plurality of outputs, wherein each of the plurality of outputs is connected to one of the Y-direction select lines. ### Claim 23 (depends on 22) The integrated circuit structure of claim 22, wherein the back-gate controller is configured to, in a write operation of a selected cell of the SRAM cells, apply a first low voltage to a selected one of the Y-direction select lines connected to the selected cell, and a high voltage to all of unselected Y-direction select lines connected to unselected ones of the SRAM cells. ### Claim 24 (depends on 23) The integrated circuit structure of claim 23, wherein the back-gate controller is further configured to, in a sleep mode operation of the SRAM cells, apply a second low voltage to all of the Y-direction select lines, and wherein the first low voltage has a voltage level higher than the second low voltage. ### Claim 25 (depends on 22) The integrated circuit structure of claim 22, wherein the back-gate controller is configured to, in a read operation of a selected one of the SRAM cells, apply a high voltage to all of the Y-direction select lines. ### Claim 26 (depends on 22) The integrated circuit structure of claim 22, wherein the back-gate controller is configured to, in a sleep mode operation of the SRAM cells, apply low voltages to all of the Y-direction select lines. ### Claim 27 (depends on 26) The integrated circuit structure of claim 26, wherein in the sleep mode operation of the SRAM cells, the low voltages applied to all of the Y-direction select lines are negative voltages.