# US 2010/0165705 A1 · Semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0165705 A1 - Document ID: US20100165705A1 - Status: Published application - Kind: A1 - Application number: 12/687,743 - Filed: 2010-01-14 - Published: 2010-07-01 - Earliest claimed: 2004-06-09 - Assignees: Panasonic Corporation - Inventors: Masaya SUMITA - Web page: https://patentgrep.com/patent/US20100165705A1 ## CPC - G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups - G06F 9/30141: {Implementation provisions of register files, e.g. ports} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits} - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 2207/104: Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 20A is dedicated to a first functional block having one first write port section 21AW and two first read port sections 21AR1 and 21AR2. A second holding circuit 30B is dedicated to a second functional block having one second write port section 31AW and one second read port section 31BR. When it is necessary to read data held in the first holding circuit 20A from the second read port section 31BR, for example, a data interchange operation is performed as follows. After the data of the second holding circuit 30B is latched in a latch circuit 40, the data of the first holding circuit 20A is transferred to the second holding circuit 30B, and then the data of the second holding circuit 30B latched in the latch circuit 40 is transferred to the first holding circuit 20A. Thus, the area necessary to provide a register file is significantly reduced. ## Claims ### Claim at position 1 1-36. (canceled) ### Claim 37 A semiconductor integrated circuit, comprising; a holding circuit having a first inverted circuit, a second inverted circuit and a first transistor; and a write port section connected to the holding circuit, wherein an output side of the first inverted circuit is connected to an input side of the second inverted circuit, an output side of the second inverted circuit is connected to an input side of the first inverted circuit, the second inverted circuit has a second transistor connected to the first transistor sequentially in series, the first transistor has the same conductivity type as the second transistor and a gate of the first transistor is connected to the write port section. ### Claim 38 (depends on 37) The semiconductor integrated circuit of claim 37, wherein the second inverted circuit includes a third transistor having a different conductivity type from the first transistor. ### Claim 39 (depends on 38) The semiconductor integrated circuit of claim 38, wherein a source of the first transistor receives an inverted signal of a signal from a write line. ### Claim 40 (depends on 38) The semiconductor integrated circuit of claim 38, wherein the write port section includes a third inverted circuit. ### Claim 41 (depends on 40) The semiconductor integrated circuit of claim 40, wherein the third inverted circuit outputs an inverted signal of a signal from a write line. ### Claim 42 (depends on 41) The semiconductor integrated circuit of claim 41, wherein the third inverted circuit includes a fourth transistor having the same conductivity type as the first transistor. ### Claim 43 (depends on 42) The semiconductor integrated circuit of claim 42, wherein an output node between the second transistor and the third transistor is grounded via the first, second and fourth transistors. ### Claim 44 (depends on 41) The semiconductor integrated circuit of claim 41, wherein a source of the first transistor receives the inverted signal from the third inverted circuit. ### Claim 45 (depends on 38) The semiconductor integrated circuit of claim 38, wherein a source of the first transistor is grounded. ### Claim 46 (depends on 38) The semiconductor integrated circuit of claim 38, wherein the output side of the second inverted circuit is connected to the write port section without inverting logic of output of the second inverted circuit. ### Claim 47 (depends on 46) The semiconductor integrated circuit of claim 46, wherein the output side of the second inverted circuit is directly connected to the write port section. ### Claim 48 (depends on 38) The semiconductor integrated circuit of claim 38, wherein the gate of the first transistor receives a signal from the write port section. ### Claim 49 (depends on 48) The semiconductor integrated circuit of claim 48, wherein a source of the first transistor receives an inverted signal of a signal from a write line. ### Claim 50 (depends on 48) The semiconductor integrated circuit of claim 48, wherein a source of the second transistor receives an inverted signal of a signal from a write line. ### Claim 51 (depends on 48) The semiconductor integrated circuit of claim 48, wherein the first transistor turns on when the signal from the write port section is Low level. ### Claim 52 (depends on 50) The semiconductor integrated circuit of claim 50, wherein the first transistor turns off when the signal from the write port section is High level. ### Claim 53 (depends on 38) The semiconductor integrated circuit of claim 38, wherein the plurality of transistors are N-channel transistors. ### Claim 54 (depends on 37) The semiconductor integrated circuit of claim 37, wherein the write port section is disabled to write data, according to a signal from a write line to the write port section. ### Claim 55 (depends on 37) The semiconductor integrated circuit of claim 37, wherein an output side of the first inverted circuit is connected to a read port section. ### Claim 56 A semiconductor integrated circuit, comprising: a holding circuit having a first inverted circuit, a second inverted circuit and a plurality of transistors; and a plurality of write port sections connected to the holding circuit, wherein an output side of the first inverted circuit is connected to an input side of the second inverted circuit, an output side of the second inverted circuit is connected to an input side of the first inverted circuit, the plurality of transistors having a same conductivity type connected sequentially in series, the second inverted circuit has a first transistor and a second transistor having a different conductivity type from the first transistor and a gate of the first transistor is connected to a gate of the second transistor, the plurality of transistors are disposed between a source of the second transistor and a ground power source, and the second transistor has the same conductivity type as the plurality of transistors. ### Claim 57 (depends on 56) The semiconductor integrated circuit of claim 56, wherein a gate of one of the plurality of transistors of which source is grounded to the ground source receives a signal from one of the plurality of write port sections that has a highest activity rate. ### Claim 58 (depends on 56) The semiconductor integrated circuit of claim 56, wherein the plurality of transistors includes a third transistor and a fourth transistor, the fourth transistor being more away from the output side of the second inverted circuit than the third transistor, and one of the write port sections to which a gate of the fourth transistor is connected has an activity rate that is higher than that of one of the write port sections to which a gate of the third transistor is connected. ### Claim 59 (depends on 56) The semiconductor integrated circuit of claim 56, wherein the output side of the second inverted circuit is connected to the plurality of write port sections. ### Claim 60 (depends on 56) The semiconductor integrated circuit of claim 56, wherein the output side of the second inverted circuit is connected to the write port section without inverting logic of output of the second inverted circuit. ### Claim 61 (depends on 60) The semiconductor integrated circuit of claim 60, wherein the output side of the second inverted circuit is directly connected to the write port section. ### Claim 62 (depends on 56) The semiconductor integrated circuit of claim 56, wherein the source of the second transistor is connected to a drain of one of the plurality of transistors. ### Claim 63 (depends on 62) The semiconductor integrated circuit of claim 62, wherein a source of other one of the plurality of transistors is connected to the ground. ### Claim 64 (depends on 56) The semiconductor integrated circuit of claim 56, wherein each gate of the plurality of transistors is corresponded to be connected to each of the plurality of write port sections. ### Claim 65 (depends on 64) The semiconductor integrated circuit of claim 64, wherein the one of the plurality of transistors turns on when a signal from the corresponding one of the plurality of the write port section is Low level. ### Claim 66 (depends on 65) The semiconductor integrated circuit of claim 65, wherein the one of the plurality of transistors turns off when the signal from the corresponding one of the plurality of the write port sections is High level. ### Claim 67 (depends on 56) The semiconductor integrated circuit of claim 56, wherein the plurality of transistors are N-channel transistors. ### Claim 68 (depends on 56) The semiconductor integrated circuit of claim 56, wherein at least one of the plurality of the write port sections is disabled to write data, according to a signal from a write line to the one of the plurality of the write port sections. ### Claim 69 (depends on 56) A semiconductor integrated circuit of claim 56, wherein an output side of the first inverted circuit is connected to a read port section. ### Claim 70 (depends on 37) A register file with multiple port having the semiconductor integrated circuit of claim 37 as a memory cell. ### Claim 71 (depends on 56) A register file with multiple port having the semiconductor integrated circuit of claim 56 as a memory cell.