# US 2010/0165704 A1 · Circuit and Method for a High Speed Memory Cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0165704 A1 - Document ID: US20100165704A1 - Status: Published application - Kind: A1 - Application number: 12/346,173 - Filed: 2008-12-30 - Published: 2010-07-01 - Earliest claimed: 2008-12-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Cheng-Hsu Wu; David Yen; Tsai-Hsin Lai - Web page: https://patentgrep.com/patent/US20100165704A1 ## CPC - G11C 11/416: Read-write [R-W] circuits - G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory cell is disclosed, including a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed. ## Claims ### Claim 1 A memory cell, comprising: a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. ### Claim 2 (depends on 1) The memory cell of claim 1, wherein the write word line is coupled to a high voltage to store charge representative of a data value in the storage capacitor. ### Claim 3 (depends on 2) The memory cell of claim 2, wherein the write access transistor has a gate terminal coupled to the write word line. ### Claim 4 (depends on 2) The memory cell of claim 2, wherein a charge representative of a “1” is stored in the storage capacitor by coupling the write bit line to a high voltage during a write cycle. ### Claim 5 (depends on 2) The memory cell of claim 2, wherein a charge representative of “O” is stored in the storage capacitor by coupling the write bit line to a low voltage during a write cycle. ### Claim 6 (depends on 2) The memory cell of claim 2, wherein when a high voltage is placed on the read word line, a voltage representative of a stored data value is placed on the read bit line by the read access transistor. ### Claim 7 (depends on 6) The memory cell of claim 6, wherein when the stored charge is representative of a “1” during a read cycle, a first voltage is placed on the read bit line and when the stored charge is representative of a “0”, a second voltage is placed on the read bit line. ### Claim 8 (depends on 6) The memory cell of claim 6, wherein during a read cycle the voltage at the gate of the read access transistor is the read word line voltage boosted by a voltage from the storage capacitor. ### Claim 9 (depends on 7) The memory cell of claim 7, wherein the difference between the first voltage and the second voltage corresponds to the threshold voltage drop of the read access transistor. ### Claim 10 (depends on 1) The memory cell of claim 1 wherein the read bit line is driven by the read access transistor during read cycles. ### Claim 11 A dynamic memory array, comprising: a plurality of dynamic memory cells arranged in rows and columns, each dynamic memory cell coupled to a respective read word line, a respective read bit line, a respective write word line, and a respective write bit line, and each dynamic memory cell further comprising: a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. ### Claim 12 (depends on 11) The dynamic memory array of claim 11, wherein the write word line is coupled to a high voltage to store charge representative of a data value in the storage capacitor. ### Claim 13 (depends on 12) The dynamic memory array of claim 12, wherein the write access transistor has a gate terminal coupled to the write word line. ### Claim 14 (depends on 12) The dynamic memory array of claim 12, wherein a charge representative of a “1” is stored in the storage capacitor by coupling the write bit line to a high voltage during a write cycle. ### Claim 15 (depends on 12) The dynamic memory array of claim 12, wherein a charge representative of “0” is stored in the storage capacitor by coupling the write bit line to a low voltage during a write cycle. ### Claim 16 (depends on 12) The dynamic memory array of claim 12, wherein when a high voltage is placed on the read word line during a read cycle, a voltage representative of a stored data value is placed on the read bit line by the read access transistor. ### Claim 17 (depends on 16) The dynamic memory array of claim 16, wherein when the stored charge is representative of a “1” during a read cycle, a first voltage is placed on the read bit line, and when the stored charge is representative of a “0”, a second voltage is placed on the read bit line. ### Claim 18 (depends on 16) The dynamic memory array of claim 16, wherein during a read cycle the voltage at the gate of the read access transistor is the read word line voltage boosted by a voltage from the storage capacitor. ### Claim 19 (depends on 18) The dynamic memory array of claim 18, wherein the difference between the first voltage and the second voltage corresponds to the threshold voltage drop of the read access transistor. ### Claim 20 (depends on 11) The dynamic memory array of claim 11 wherein the read bit line is driven by the read access transistor during read cycles.