# US 2010/0165702 A1 · Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0165702 A1 - Document ID: US20100165702A1 - Status: Published application - Kind: A1 - Application number: 12/559,178 - Filed: 2009-09-14 - Published: 2010-07-01 - Earliest claimed: 2005-09-01 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Haruki TODA - Web page: https://patentgrep.com/patent/US20100165702A1 ## CPC - G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]} - G11C 13/0069: {Writing or programming circuits or methods} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - G11C 2013/009: {Write using potential difference applied between cell electrodes} - G11C 2213/15: Current-voltage curve - G11C 2213/71: Three dimensional array - G11C 2213/72: Array wherein the access device being a diode - H10N 70/245: {the species being metal cations, e.g. programmable metallization cells} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8822: {Sulfides, e.g. CuS} - H10N 70/8825: {Selenides, e.g. GeSe} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array. ## Claims ### Claim 1 A programmable resistance memory device comprising: a semiconductor substrate; at least one cell array, formed above the semiconductor substrate, which comprises a plurality of bit lines arranged in parallel with each other, a plurality of word lines arranged in parallel with each other in such a direction as crossing said bit lines, and memory cells connected between the bit lines and the word lines at cross points of the bit lines and word lines, each said memory cell comprising a programmable resistance element which stores the high resistance state or the low resistance state in a non-volatile manner; and a read/write circuit formed on the semiconductor substrate as underlying said cell array and connected to the bit lines and word lines through vertical wirings for data reading and data writing in communication with said cell array, said read/write circuit comprising a first select gate circuit for selecting one of said vertical wirings to apply a drive voltage to a selected bit line or a selected word line connected to a selected memory cell via the selected vertical wiring for data reading and writing, and a second select gate circuit for selecting non-selected vertical wirings to apply a hold voltage to non-selected bit lines or non-selected word lines via non-selected vertical wirings, said first select gate circuit being arranged in one side of a boundary which is formed by read/write circuit side contact ends of the vertical wirings, and said second select gate circuit being arranged in the other side of the boundary. ### Claim 2 (depends on 1) The programmable resistance memory device according to claim 1, wherein the memory cell comprises an access element connected in series to said programmable resistance element, said access element having a resistance value in an off-state that is ten time more as high as that in a select state. ### Claim 3 (depends on 1) The programmable resistance memory device according to claim 1, wherein said programmable resistance element being applied said drive voltage greater than a certain threshold to develop a high resistance state or a low resistance state. ### Claim 4 (depends on 1) The programmable resistance memory device according to claim 1 wherein, said programmable resistance element comprises an ion conductor containing metal ions with anode and cathode electrodes sandwiching said ion conductor. ### Claim 5 (depends on 1) The programmable resistance memory device according to claim 1, wherein said programmable resistance element comprises a polymer, in which conductive particles are dispersed, with anode and cathode electrodes sandwiching said polymer. ### Claim 6 (depends on 2) The programmable resistance memory device according to claim 2, wherein the access element is a diode selected from a Zener diode, a PN junction diode and a Shottky diode. ### Claim 7 (depends on 6) The programmable resistance memory device according to claim 6, wherein: said memory cells are arranged on the bit lines at a certain pitch in a direction of an extension of a bit line, and said each word line is commonly connected with the upper ends of said memory cells in such a direction as crossing said bit lines. ### Claim 8 (depends on 7) The programmable resistance memory device according to claim 7 wherein, said programmable resistance element and said diode serving as said access element of each said memory cell are stacked in such a manner that the respective anodes of said programmable resistance element and said diode are connected to said bit line and word line, respectively. ### Claim 9 (depends on 8) The programmable resistance memory device according to claim 8, wherein a plurality of cell arrays are stacked in such a manner that at least one of said bit lines and word lines are shared with adjacent two cell arrays. ### Claim 10 (depends on 9) The programmable resistance memory device according to claim 9, wherein: the vertical wirings comprises first, second and third wirings, said first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of said cell arrays in the direction of said bit lines to connect said bit lines of the respective cell arrays to said read/write circuit, and said third vertical wirings disposed outside of one of third and fourth boundaries that define said cell layout region in the direction of said word lines to connect said word lines of the respective cell arrays to said rd/write circuit. ### Claim 11 (depends on 10) The programmable resistance memory device according to claim 10, wherein said first to third wirings are formed of contact plugs which are buried in an insulator layer formed surround said cell arrays. ### Claim 12 (depends on 6) The programmable resistance memory device according to claim 6, wherein: said drive voltage includes a first write voltage and a second write voltage, and said read/write circuit is configured to apply said first write voltage to a selected one of said memory cells to cause a diode thereof serving as said access element forward bias, thereby setting the programmable resistance element thereof at the low resistance state, and to apply said second write voltage with polarity opposite to said first write voltage to the selected one of said memory cell to cause a diode thereof serving as said access element breakdown, thereby setting the programmable resistance element thereof at the high resistance state. ### Claim 13 (depends on 12) The programmable resistance memory device according to claim 12 wherein: said drive voltage includes a read voltage, and said read/drive circuit is configured to apply said read voltage lower than said first write voltage to the selected one of said memory cells to cause a diode thereof serving as said access element forward bias, thereby detecting a data state of the programmable resistance element thereof. ### Claim 14 (depends on 8) The programmable resistance memory device according to claim 8, wherein: said drive voltage includes a first write voltage and a second write voltage, and said read/write circuit is configured to apply said first write voltage to a selected one of said memory cells through a selected bit line and a selected word line to cause a diode thereof serving as said access element forward bias, thereby setting the programmable resistance element thereof at the low resistance state, and to apply said second write voltage with a polarity opposite to said first write voltage to the selected one of said memory cells through a selected bit line and a selected word line to cause a diode thereof serving as said access element breakdown, thereby setting the programmable resistance element thereof at the high resistance state. ### Claim 15 (depends on 14) The programmable resistance memory device according to claim 14, wherein: said drive voltage includes a read voltage, and said read/write circuit is configured to apply said read voltage lower than said first write voltage to the selected one of said memory cells through a selected bit line and a selected word line to cause a diode thereof serving as said access element forward bias, thereby detecting a data state of the programmable resistance element thereof. ### Claim 16 (depends on 15) The programmable resistance memory device according to claim 15, wherein said read/write circuit is configured to apply said hold voltage between said bit lines and word lines in a non-select state to hold said diodes of said memory cells at a high impedance off-state with a reverse bias. ### Claim 17 (depends on 9) The programmable resistance memory device according to claim 9, wherein neighboring two memory cells in each said plurality of cell arrays constitute a pair cell for storing complementary data one of which is the high resistance state, and the other is the low resistance state, and wherein said complementary data of said pair cell are read out to a bit line pair as one bit of data. ### Claim 18 (depends on 17) The programmable resistance memory device according to claim 17, wherein two memory cells constituting said pair cell are laterally neighboring in each of said plurality of cell arrays in such a manner that anodes of diodes thereof are commonly connected to one of said word lines and anodes of programmable resistance elements thereof are connected to a pair of bit lines. ### Claim 19 (depends on 17) The programmable resistance memory device according to claim 17, wherein one bit line of said pair of bit lines to which said complementary data are read out to disposed between bit lines of another pair of bit lines to which another complementary data are read out. ### Claim 20 (depends on 17) The programmable resistance memory device according to claim 17 wherein two memory cells constituting said pair cell are vertically neighboring between neighboring two cell arrays in said plurality of cell arrays in such a manner that anodes of diodes thereof are commonly connected to one of said word lines shared by said two cell arrays, and anodes of programmable resistance elements thereof are connected to bit lines disposed at said two cell arrays, respectively.