# US 2010/0164941 A1 · Spread spectrum clocking interface apparatus of flat panel display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164941 A1 - Document ID: US20100164941A1 - Status: Published application - Kind: A1 - Application number: 12/636,026 - Filed: 2009-12-11 - Published: 2010-07-01 - Earliest claimed: 2008-12-29 - Inventors: Jong-Seok Chae - Web page: https://patentgrep.com/patent/US20100164941A1 ## CPC - H04B 15/02: Reducing interference from electric apparatus by means located at or near the interfering apparatus - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation - H04B 2215/067: by modulation dispersion - H04B: TRANSMISSION - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A spread spectrum clocking interface apparatus of a flat panel display for compensating for a frequency difference between a first clock signal externally supplied to a timing controller and a second clock signal generated from a spread spectrum clocking unit. The spread spectrum clocking interface apparatus includes a storage unit, first and second counters, and a delay unit. The storage unit stores input data to be supplied to the flat panel display in a first-in/first-out (FIFO) manner in accordance with a write address and outputs the stored input data in the FIFO manner in accordance with a read-out address. The first counter counts the first clock signal in response to a display enable signal and outputs a result of the counting as the write address. The delay unit delays the display enable signal while the second counter counts the second clock signal in response to the delayed display enable signal and outputs a result of the counting of the second counter as the read-out address. ## Claims ### Claim 1 A spread spectrum clocking interface apparatus of a flat panel display which compensates for a frequency difference between a first clock signal externally supplied to a timing controller and a second clock signal generated from a spread spectrum clocking unit, the spread spectrum clocking interface apparatus comprising: a storage unit which stores input data to be supplied to the flat panel display in a first-in/first-out (FIFO) manner in accordance with a write address, and outputs the stored input data in the FIFO manner in accordance with a read-out address; a first counter which counts the first clock signal in response to a display enable signal, and outputs a result of the counting as the write address; a delay unit which delays the display enable signal; and a second counter which counts the second clock signal in response to the delayed display enable signal, and outputs a result of the counting of the second counter as the read-out address. ### Claim 2 (depends on 1) The spread spectrum clocking interface apparatus of claim 1, wherein the delay unit delays the display enable signal for a predetermined time determined in accordance with a number of the input data and the first clock signal. ### Claim 3 (depends on 2) The spread spectrum clocking interface apparatus of claim 2, wherein a maximum delay time of the display enable signal delayed by the delay unit is expressed as: τ max = ( T   1 - T   2 ) × D T   1 where τmax represents the maximal delay time, D represents the number of the input data, T1 represents a period of the first clock signal, and T2 represents a period of the second clock signal. ### Claim 4 (depends on 1) The spread spectrum clocking interface apparatus of claim 1, wherein the storage unit comprises n FIFO units each connected to the input data to store the input data when the FIFO unit is designated by the write address, and to read out the input data when the FIFO unit is designated by the read-out address. ### Claim 5 (depends on 4) The spread spectrum clocking interface apparatus of claim 4, wherein a maximum value of n is expressed as: n max = ( T   1 - T   2 ) × 2  D T   1 where nmax represents the maximal value of n, D represents a number of data contained in the input data, T1 represents a period of the first clock signal, and T2 represents a period of the second clock signal. ### Claim 6 (depends on 1) The spread spectrum clocking interface apparatus of claim 1, wherein the flat panel display comprises a liquid display panel. ### Claim 7 (depends on 6) The spread spectrum clocking interface apparatus of claim 6, wherein the input data stored in the storage unit in accordance with the write address generated in response to the display enable signal corresponds to data for one horizontal line to be displayed on the liquid crystal display panel. ### Claim 8 A spread spectrum clocking interface apparatus of a flat panel display which compensates for a frequency difference between a first clock signal externally supplied to a timing controller and a second clock signal generated from a spread spectrum clocking unit, the spread spectrum clocking interface apparatus comprising: a storage unit which stores input data to be supplied to the flat panel display in a first-in/first-out (FIFO) manner in accordance with a write address; a first counter which counts the first clock signal in response to a display enable signal; a delay unit which delays the display enable signal; and a second counter which counts the second clock signal in response to the delayed display enable signal. ### Claim 9 (depends on 8) The spread spectrum clocking interface apparatus of claim 8, wherein the storage unit outputs the stored input data in the FIFO manner in accordance with a read-out address. ### Claim 10 (depends on 9) The spread spectrum clocking interface apparatus of claim 9, wherein the second counter outputs a result of the counting of the second counter as the read-out address. ### Claim 11 (depends on 9) The spread spectrum clocking interface apparatus of claim 9, wherein the first counter outputs a result of the counting as the write address. ### Claim 12 (depends on 8) The spread spectrum clocking interface apparatus of claim 8, wherein the delay unit delays the display enable signal for a predetermined time. ### Claim 13 (depends on 12) The spread spectrum clocking interface apparatus of claim 12, wherein the predetermined time is determined in accordance with a number of the input data and the first clock signal. ### Claim 14 (depends on 13) The spread spectrum clocking interface apparatus of claim 13, wherein a maximum delay time of the display enable signal delayed by the delay unit is expressed as: τ max = ( T   1 - T   2 ) × D T   1 where τmax represents the maximal delay time, D represents the number of the input data, T1 represents a period of the first clock signal, and T2 represents a period of the second clock signal. ### Claim 15 (depends on 10) The spread spectrum clocking interface apparatus of claim 10, wherein the storage unit comprises n FIFO units each connected to the input data. ### Claim 16 (depends on 15) The spread spectrum clocking interface apparatus of claim 15, wherein the n FIFO units store the input data when the FIFO unit is designated by the write address. ### Claim 17 (depends on 16) The spread spectrum clocking interface apparatus of claim 16, wherein the n FIFO units reads out the input data when the FIFO unit is designated by the read-out address. ### Claim 18 (depends on 17) The spread spectrum clocking interface apparatus of claim 17, wherein a maximum value of n is expressed as: n max = ( T   1 - T   2 ) × 2  D T   1 where nmax represents the maximal value of n, D represents a number of data contained in the input data, T1 represents a period of the first clock signal, and T2 represents a period of the second clock signal. ### Claim 19 (depends on 8) The spread spectrum clocking interface apparatus of claim 8, wherein the flat panel display comprises a liquid display panel. ### Claim 20 (depends on 19) The spread spectrum clocking interface apparatus of claim 19, wherein the input data stored in the storage unit in accordance with the write address generated in response to the display enable signal corresponds to data for one horizontal line to be displayed on the liquid crystal display panel.