# US 2010/0164853 A1 · Data transmission apparatus

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- Number: US 2010/0164853 A1
- Document ID: US20100164853A1
- Status: Published application
- Kind: A1
- Application number: 12/635,560
- Filed: 2009-12-10
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Assignees: Dongbu HiTek Co., Ltd.
- Inventors: Sang-Seob Kim
- Web page: https://patentgrep.com/patent/US20100164853A1

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12})
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
- G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A data transmission apparatus may include a delay locked loop for generating multi-phase clock signals synchronized to an input clock signal. A clock selector may select the multi-phase clock signals in response to a selection signal. A modulation controller may generate the selection signal using the input clock signal and modulation information, so that the clock selector selects the multi-phase clock signals within every predetermined interval. A clock generator may generate first and second latch clock signals according to the selected multi-phase clock signals. A data transmitter may transmit input data using the first and second latch clock signals. Therefore, the data transmission apparatus mitigates at least as much EMI as a related data transmission apparatus using spread spectrum clock generation for EMI mitigation, eliminates the probability of data error, and saves an IC area. It obviates the need for a FIFO memory, thus contributing miniaturization of the IC. The spread spectrum clock generation function of the related data transmission apparatus may be implemented inside the IC, thus increasing throughput.

## Claims

### Claim 1

An apparatus comprising:
a delay locked loop for generating multi-phase clock signals synchronized to an input clock signal;
a clock selector for selecting the multi-phase clock signals in response to a selection signal;
a modulation controller for generating the selection signal using the input clock signal and modulation information, so that the clock selector selects the multi-phase clock signals within every predetermined interval;
a clock generator for generating first and second latch clock signals according to the selected multi-phase clock signals; and
a data transmitter for transmitting input data using the first and second latch clock signals.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the modulation controller includes an N-bit counter.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the N-bit counter counts pulses of the input clock signal up to N bits, with N being determined according to the modulation information.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the modulation controller includes a state machine.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the state machine changes among as many states as determined according to the modulation information based on the count received from the N-bit counter.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the clock generator includes a first SR flip-flop and a second SR flip-flop.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the first SR flip-flop includes a reset terminal for receiving reset components of clock signals having fixed phases among the selected multi-phase clock signals, a set terminal for receiving set components of the clock signals having the fixed phases, and a positive output terminal for outputting the first latch clock signal.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the second SR flip-flop includes a reset terminal for receiving reset components of clock signals having phases reflecting the modulation information among the selected multi-phase clock signals, a set terminal for receiving set components of the clock signals having the phases reflecting the modulation information, and a positive output terminal for outputting the second latch clock signal.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the data transmitter includes:
a first D flip-flop and a second D flip-flop.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the first D flip-flop outputs the input data in response to the first latch clock signal.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the second D flip-flop outputs the output of the first D flip-flop as output data in response to the second latch clock signal.

### Claim 12 (depends on 2)

The apparatus of claim 2, wherein the N-bit counter counts the number of rising edges of the input clock signal as the number of pulses of the input clock signal.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the data transmission apparatus is included in a timing controller of a flat panel display.

### Claim 14

A method comprising:
generating multi-phase clock signals synchronized to an input clock signal;
selecting the multi-phase clock signals in response to a selection signal;
generating the selection signal using the input clock signal and modulation information, so that the multi-phase clock signals are selected within every predetermined interval;
generating first and second latch clock signals according to the selected multi-phase clock signals; and
transmitting input data using the first and second latch clock signals.

### Claim 15 (depends on 14)

The method of claim 14, including counting pulses of the input clock signal up to N bits, with N being determined according to the modulation information.

### Claim 16 (depends on 14)

The method of claim 14, including:
receiving reset components of clock signals having fixed phases among the selected multi-phase clock signals;
receiving set components of the clock signals having the fixed phases; and
outputting a first latch clock signal.

### Claim 17 (depends on 16)

The method of claim 16, including:
receiving reset components of clock signals having phases reflecting the modulation information among the selected multi-phase clock signals;
receiving set components of the clock signals having the phases reflecting the modulation information; and
outputting a second latch clock signal.

### Claim 18 (depends on 17)

The method of claim 17, including latching and outputting the input data in response to the first latch clock signal.

### Claim 19 (depends on 18)

The method of claim 18, including latching and outputting the previously latched and output data in response to the second latch clock signal.

### Claim 20 (depends on 14)

The method of claim 14, including counting the number of rising edges of the input clock signal as the number of pulses of the input clock signal.