# US 2010/0164779 A1 · Charge-domain pipelined charge-redistribution analog-to-digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164779 A1 - Document ID: US20100164779A1 - Status: Published application - Kind: A1 - Application number: 12/723,019 - Filed: 2010-03-12 - Published: 2010-07-01 - Earliest claimed: 2007-03-05 - Assignees: Kenet, Inc. - Inventors: Michael P. Anthony - Web page: https://patentgrep.com/patent/US20100164779A1 ## CPC - H03M 1/1245: {Details of sampling arrangements or methods} - H03M 1/44: Sequential comparisons in series-connected stages with change in value of analogue signal - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially similar to the charge input to said stage. ## Claims ### Claim 1 An analog-to-digital converter apparatus comprising: a first stage comprising: a first charge storage device, for storing an input charge that corresponds to an analog input signal; a first comparator, for comparing a reference voltage against a voltage corresponding to the input charge as stored at the first charge storage device, and in response thereto, providing a first comparison signal; a first digital storage device, for storing the first comparison signal and to provide a first digital output signal; and a first charge transfer device, for transferring the stored input charge out of the first stage; a second stage comprising: a second charge storage device for storing the stored input charge as received from the first charge transfer device of the first stage, a charge redistribution device, the charge redistribution device providing a redistribution charge that depends on the first comparison signal; a second comparator, for comparing a reference voltage with the stored input charge and the redistribution charge, to provide a second comparison signal; and a second digital storage device, for storing the second comparison signal and to provide a second digital output signal. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein at least one of the first and second charge storage devices is a capacitive circuit element. ### Claim 3 (depends on 2) The apparatus of claim 2 wherein the charge redistribution device comprises a capacitive circuit element. ### Claim 4 (depends on 3) The apparatus of claim 3 wherein the charge redistribution device further comprises a driver circuit coupled to the capacitive circuit element. ### Claim 5 (depends on 1) The apparatus of claim 1 wherein the second charge storage device is a capacitor having a first terminal coupled to receive the input charge and a second terminal coupled to receive a clock signal. ### Claim 6 (depends on 1) The apparatus of claim 1 wherein the first digital storage device is a clocked digital latch storing a first bit of an analog-to-digital conversion result. ### Claim 7 (depends on 1) The apparatus of claim 1 wherein the second digital storage device is a clocked digital latch storing a second bit of an analog-to-digital conversion result. ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising: a third stage comprising: a third charge storage device for storing the stored input charge as received from the second charge transfer device of the second stage; a second charge redistribution device, the second charge redistribution device providing a second redistribution charge that depends on the first and second comparison signal from, respectively, the first and second comparator in the first and second stages; a third comparator, for comparing a reference voltage with the stored input charge and the second redistribution charge, to provide a third comparison signal; and a third digital storage device, for storing the third comparison signal and to provide a third digital output signal. ### Claim 9 (depends on 8) The apparatus of claim 8 wherein the second charge redistribution device further comprises: a second charge redistribution capacitor coupled to a second common node, the second charge redistribution capacitor providing a charge that depends on the first comparison signal; and a third charge redistribution capacitor, coupled to the second common node, the third charge redistribution capacitor providing a charge that depends on the second comparison signal. ### Claim 10 A method for converting an analog input to digital outputs comprising: storing an input charge at a first charge storage device, the input charge corresponding to the analog input; a first step of comparing the stored input charge to a reference, to provide a first comparison result, the first comparison result also providing a first digital output; transferring the stored input charge to a second charge storage device; transferring a redistribution charge to a third charge storage device, the redistribution charge depending on the first step of comparing; and a second step of comparing charge stored by the second charge storage device and the third charge storage device against a reference, to provide a second comparison result, the second comparison result providing a second digital output. ### Claim 11 (depends on 10) The method of claim 10 further comprising: storing the first comparison result in a digital storage device. ### Claim 12 (depends on 11) The method of claim 11 further comprising: storing the second comparison result in a digital storage device. ### Claim 13 (depends on 10) The method of claim 10 wherein the step of storing an input charge further comprises storing the input charge in a first capacitive circuit element. ### Claim 14 (depends on 11) The method of claim 11 wherein the step of storing an input charge further comprises clocking the first capacitive circuit element. ### Claim 15 (depends on 10) The method of claim 10 wherein the step of transferring the input charge to a second charge storage device further comprises storing the input charge in a second capacitive circuit element. ### Claim 16 (depends on 15) The method of claim 15 wherein the step of transferring the input charge to a second charge storage device further comprises clocking the second capacitive circuit element. ### Claim 17 (depends on 16) The method of claim 16 wherein the step of transferring a redistribution charge further comprises storing the input charge in a third capacitive circuit element. ### Claim 18 (depends on 17) The method of claim 17 wherein the step of transferring a redistribution charge further comprises coupling the second and third capacitive circuit elements to a common node. ### Claim 19 (depends on 18) The method of claim 18 wherein the second step of comparing charge further comprises comparing a voltage at the common node to the reference. ### Claim 20 A method for analog-to-digital conversion in a multiple stage pipeline comprising: at a first stage of the pipeline: storing an input charge that corresponds to an analog input signal; a first comparing step of comparing a reference voltage against a voltage corresponding to the stored input charge; providing a first comparison signal in response to the first comparing step; storing the first comparison signal to provide a first digital output signal; transferring the stored input charge to a subsequent stage of the pipeline; redistributing a redistribution charge that depends on the first comparison signal; and at the subsequent stage of the pipeline: a second step of storing the stored input charge as received from the first stage of the pipeline, receiving the redistribution charge from the first stage; a second comparing step of comparing a reference voltage with a combined charge corresponding to the stored input charge and the redistribution charge, to provide a second comparison signal; and storing the second comparison signal to provide a second digital output signal.