# US 2010/0164775 A1 · Digital-analog conversion device and method for the digital-analog conversion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164775 A1 - Document ID: US20100164775A1 - Status: Published application - Kind: A1 - Application number: 12/642,111 - Filed: 2009-12-18 - Published: 2010-07-01 - Earliest claimed: 2008-12-30 - Assignees: Dongbu HiTek Co., Ltd. - Inventors: Tae-Woon Kim; Shin-Young Yi; Sang-Hoon Lim; Jin-Seok Koh - Web page: https://patentgrep.com/patent/US20100164775A1 ## CPC - H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits - H03M 1/76: using switching tree - H03M 3/50: {Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004)} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A digital-analog conversion circuit, a method for the digital-analog conversion and a source driver are disclosed. A digital-analog conversion circuit may include a latch for storing N bit digital data therein, and a digital-analog converter, for performing a first digital-analog conversion on predetermined bits out of the N bit data stored in the latch by using R-string conversion, and for performing a second digital-analog conversion based on a result of the first digital-analog conversion and all remaining bits of the N bit data, excluding the predetermined bits. ## Claims ### Claim 1 An apparatus comprising: a latch for storing N bit digital data therein, wherein N is a positive real number; and a digital-analog converter, for performing a first digital-analog conversion on predetermined bits out of the N bit data stored in the latch by using R-string conversion, and for performing a second digital-analog conversion based on a result of the first digital-analog conversion and all remaining bits of the N bit data, excluding the predetermined bits. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the digital-analog converter comprises an R-string DAC for performing the first digital-analog conversion based on M bit data, wherein the M bit data is the predetermined bits which include a high-order subset of the N bit data stored in the latch. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the digital-analog converter comprises a delta-sigma DAC for performing the second digital-analog conversion based on remaining N-M bit data and the result of the first digital-analog conversion, wherein the remaining N-M bit data is all lower order N bit data excluding the high-order M bit data. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the R-string DAC generates a first reference voltage and a second reference voltage based on the M bit data. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the delta-sigma DAC outputs an analog signal, based on the N-M bit data, using the first and second reference voltages as reference voltages. ### Claim 6 (depends on 2) The apparatus of claim 2, wherein N is 10 and M is 3. ### Claim 7 (depends on 2) The apparatus of claim 2, wherein the R-string DAC includes a plurality of resistors connected in series between a first R-string driving voltage and a second R-string driving voltage. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein connections between the resistors form a series of nodes, and the R-string DAC includes a switch connected to each of the nodes. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the switch outputs a first reference voltage and a second reference voltage based on the high-order M bit data. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the first reference voltage and a second reference voltage are fractional values of the voltage difference between first R-string driving voltage and the second R-string driving voltage. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the denominator of the fractional values is based on the number of resistors in the R-string. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the denominator of the fractional values is 2M. ### Claim 13 A method comprising: storing N bit digital data, wherein N is a positive real number; performing a first digital-analog conversion, using R-string conversion, based on predetermined bits out of the stored N bit data; and performing a second digital-analog conversion, using delta-sigma conversion, based on a result of the first digital-analog conversion and all remaining bits of the N bit data, excluding the predetermined bits. ### Claim 14 (depends on 13) The method of claim 13, wherein performing the first digital-analog conversion generates a first reference voltage and a second reference voltage based on M bit data, wherein the M bit data is the predetermined bits, which are a high-order subset of the stored N bit data. ### Claim 15 (depends on 14) The method of claim 14, wherein performing the second digital-analog conversion outputs an analog signal using the delta-sigma conversion, based on remaining N-M bit data, wherein the remaining N-M bit data is all lower order N bit data excluding the high-order M bit data, using the first and second reference voltages as reference voltage. ### Claim 16 An apparatus comprising: a latch for storing N bit digital data therein, wherein N is a positive real number; a digital-analog converter, for performing a first digital-analog conversion on predetermined bits out of the N bit data stored in the latch by using R-string conversion, and for performing a second digital-analog conversion based on a result of the first digital-analog conversion and remaining bits, not including the predetermined bits, out of the N bit data; and an output buffer for buffering the analog signal and for outputting the result of the buffering. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the digital-analog converter includes: an R-string DAC for performing the first digital-analog conversion based on M bit data, wherein the M bit data is the predetermined bits which include a high-order subset of the N bit data stored in the latch; and a delta-sigma DAC for performing the second digital-analog conversion based on remaining N-M bit data and the result of the first digital-analog conversion, wherein the remaining N-M bit data is all lower order N bit data excluding the high-order M bit data. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the R-string DAC generates a first reference voltage and a second reference voltage based on the M bit data. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the delta-sigma DAC outputs an analog signal, based on the N-M bit data, using the first and second reference voltages as reference voltages. ### Claim 20 (depends on 17) The apparatus of claim 17, wherein the R-string DAC includes a plurality of resistances connected in series between a first R-string driving voltage and a second R-string driving voltage.