Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing

A dual-input differential amplifier comprising:

• first current source means for generating a first current;
• first primary differential transistor means, having a gate receiving a non-inverting input, for conducting a portion of the first current to an inverting output;
• second primary differential transistor means, having a gate receiving an inverting input, for conducting a portion of the first current to a non-inverting output;
• second current source means for generating a second current;
• first secondary differential transistor means, having a gate receiving a non-inverting feedback input, for conducting a portion of the second current to the inverting output;
• second secondary differential transistor means, having a gate receiving an inverting feedback input, for conducting a portion of the second current to the non-inverting output;
• inverting current sink transistor means for conducting a first sink current from the inverting output in response to a first sink gate;
• and
• non-inverting current sink transistor means for conducting a second sink current from the non-inverting output in response to a second sink gate.

A Successive-Approximation-Register Analog-to-Digital Converter (SARADC) comprising:

• an analog input having an analog input voltage;
• a Successive-Approximation-Register (SAR) having a digital value that is successively adjusted to converge to closer approximations of the analog input voltage;
• a digital-to-analog converter (DAC), receiving a reference voltage and the digital value from the SAR, the DAC generating a converted analog voltage represented by the digital value;
• a series of stages including a first stage and a final stage, the first stage receiving the converted analog voltage and the analog input voltage as stage inputs, the final stage outputting compare results as stage outputs, wherein each intermediate stage in the series of stages has stage inputs coupled to stage outputs of a prior stage and stage outputs connected to stage inputs of a following stage;
• wherein the stage outputs comprise an inverting output and a non-inverting output;
• wherein the SAR adjusts the digital value based on the compare results;
• wherein each stage in the series of stages comprises:
• a first input switch that connects a first one of the stage inputs to an inverting input in response to a second clock;
• a second input switch that connects a second one of the stage inputs to a non-inverting input in response to the second clock;
• a first current source generating a first current;
• a first primary differential transistor, having a gate receiving the non-inverting input, that conducts a portion of the first current to the inverting output;
• a second primary differential transistor, having a gate receiving an inverting input, that conducts a portion of the first current to the non-inverting output;
• a second current source that generates a second current;
• a first secondary differential transistor, having a gate receiving a non-inverting feedback input, that conducts a portion of the second current to the inverting output;
• a second secondary differential transistor, having a gate receiving an inverting feedback input, that conducts a portion of the second current to the non-inverting output;
• an inverting current sink transistor that conducts a first sink current from the inverting output in response to a first sink gate;
• a non-inverting current sink transistor that conducts a second sink current from the non-inverting output in response to a second sink gate;
• a first feedback switch that connects the non-inverting feedback input to the non-inverting output in response to a first clock;
• a second feedback switch that connects the inverting feedback input to the inverting output in response to the first clock;
• and
• an offset capacitor that stores an offset charge between the inverting feedback input and the non-inverting feedback input.