# US 2010/0164735 A1 · System And Method For Testing Power Transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164735 A1 - Document ID: US20100164735A1 - Status: Published application - Kind: A1 - Application number: 12/634,141 - Filed: 2009-12-09 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: Caterpillar Inc. - Inventors: Mark E. Hartman; James D. Siegle; Thuong D. Le; Bruce H. Hein - Web page: https://patentgrep.com/patent/US20100164735A1 ## CPC - G01R 31/42: AC power supplies - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A method for testing a power converter having at least one power transistor is disclosed. The method may include receiving a power transistor test request, and resetting a fault flag. The method may also include applying a gate driver signal to each power transistor, receiving a feedback signal from each power transistor, and determining a difference between the gate driver signal and the feedback signal associated with a respective power transistor. The method may further include identifying a fault if the difference exceeds a threshold profile, and setting a fault flag when a fault is identified. ## Claims ### Claim 1 A method for testing a power converter having at least one power transistor, comprising: receiving a power transistor test request; resetting a fault flag for each power transistor, wherein the fault flag indicates a fault status associated with a corresponding power transistor; applying a gate driver signal to each power transistor; receiving a feedback signal from each power transistor; determining a difference between the gate driver signal and the feedback signal associated with a respective power transistor; determining whether the feedback signal received is a non-zero waveform over a predetermined period of time; and identifying a power transistor fault if the difference exceeds a threshold profile and the feedback signal received is a non-zero waveform over the predetermined period of time. ### Claim 2 (depends on 1) The method of claim 1, further including identifying an open circuit fault if the difference exceeds a threshold profile and the feedback signal received is a zero waveform over the predetermined period of time. ### Claim 3 (depends on 1) The method of claim 1, further including setting the fault flag for the power transistor on which a power transistor fault is identified. ### Claim 4 (depends on 1) The method of claim 1, wherein the predetermined period of time is a full signal switch period. ### Claim 5 (depends on 1) The method of claim 1, wherein the test request is initiated by a user via a user interface. ### Claim 6 (depends on 1) The method of claim 1, wherein the test request is initiated at the start of the machine. ### Claim 7 (depends on 1) The method of claim 1, wherein resetting a fault flag further includes disabling an operation of the power converter. ### Claim 8 (depends on 1) The method of claim 1, wherein the difference includes a difference between a waveform of the gate driver signal and a waveform of the feedback signal. ### Claim 9 (depends on 1) The method of claim 1, wherein the difference includes a time delay between the gate driver signal and the feedback signal. ### Claim 10 (depends on 1) The method of claim 1, wherein identifying the power transistor fault further includes diagnosing the power transistor fault and determining a type and a location of the fault. ### Claim 11 (depends on 7) The method of claim 7, wherein the type of the fault includes at least one of a device fault, a driving circuit fault, and a wiring fault. ### Claim 12 (depends on 1) The method of claim 1, wherein the at least one power transistor is an insulated gate bipolar transistor. ### Claim 13 (depends on 3) The method of claim 3, wherein setting the fault flag further includes: generating a test report having a fault advisory message; and displaying the test report on a display device. ### Claim 14 (depends on 13) The method of claim 13, wherein the fault advisory message contains information associated with a type and a location of each power transistor fault. ### Claim 15 (depends on 3) The method of claim 3, wherein setting the fault flag further includes providing at least one warning indication in response to a power transistor fault. ### Claim 16 (depends on 1) The method of claim 1, further including enabling an operation of the power converter if no fault is identified. ### Claim 17 A power transistor testing system, comprising: a controller electrically coupled to a power converter, and being configured to: reset a fault flag for each power transistor, wherein the fault flag indicates a fault status associated with a corresponding power transistor; apply a gate driver signal to each power transistor; receive a feedback signal from each power transistor; determine a difference between the gate driver signal and the feedback signal associated with a respective power transistor; determine whether the feedback signal received is a non-zero waveform over a predetermined period of time; and identify a power transistor fault if the difference exceeds a threshold profile and the feedback signal received is a non-zero waveform over the predetermined period of time; and a display device coupled to the controller, and being configured to provide at least one warning indication in the event of a power transistor fault. ### Claim 18 (depends on 17) The power transistor testing system of claim 17, wherein the controller is further configured to identify an open circuit fault if the difference exceeds a threshold profile and the feedback signal received is a zero waveform over the predetermined period of time. ### Claim 19 (depends on 18) The power transistor testing system of claim 18, wherein the display device is further configured to provide at least one warning indication in the event of an open circuit fault. ### Claim 20 (depends on 17) The power transistor testing system of claim 17, further including a user interface, configured to: receive a power transistor test request; and receive a threshold profile for each power transistor. ### Claim 21 (depends on 17) The power transistor testing system of claim 17, wherein the difference includes a difference between a waveform of the gate driver signal and a waveform of the feedback signal. ### Claim 22 (depends on 17) The power transistor testing system of claim 17, wherein the difference includes a time delay between the gate driver signal and the feedback signal. ### Claim 23 (depends on 17) The power transistor testing system of claim 17, wherein the controller is further configured to: diagnose power transistor fault and determining a type and a location of the fault; and generating a test report having a fault advisory message which contains the type and the location of the fault. ### Claim 24 (depends on 23) The power transistor testing system of claim 23, wherein the display device is further configured to display the test report. ### Claim 25 A machine, comprising: a power source; at least one power converter, each power converter having at least one power transistor; and a power transistor testing system electrically coupled to the at least one power converter, wherein the power transistor testing system includes: a controller electrically coupled to the at least one power converter, and being configured to: apply a gate driver signal to each power transistor; receive a feedback signal from each power transistor; determine a difference between the gate driver signal and the feedback signal associated with a respective power transistor; and determine whether the feedback signal received is a non-zero waveform over a predetermined period of time; identify a power transistor fault if the difference exceeds a threshold profile and the feedback signal received is a non-zero waveform over the predetermined period of time; and a display device configured to provide at least one warning indication if a power transistor fault is detected. ### Claim 26 (depends on 25) The machine of claim 25, wherein the controller is further configured to identify an open circuit fault if the feedback signal received is a zero waveform over the predetermined period of time. ### Claim 27 (depends on 26) The machine of claim 26, wherein the display device is configured to provide at least one warning indication if an open circuit fault is detected. ### Claim 28 (depends on 25) The machine of claim 25, wherein the power transistor testing system further includes a user interface configured to: receive a power transistor test request; and receive a threshold profile for each power transistor.