# US 2010/0164618 A1 · Feedback network for cascaded amplifiers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164618 A1 - Document ID: US20100164618A1 - Status: Published application - Kind: A1 - Application number: 12/345,609 - Filed: 2008-12-29 - Published: 2010-07-01 - Earliest claimed: 2008-12-29 - Inventors: Esa Tiiliharju - Web page: https://patentgrep.com/patent/US20100164618A1 ## CPC - H03F 1/342: {in field-effect transistor amplifiers} - H03F 3/3022: {CMOS common source output SEPP amplifiers (H03F3/3008 takes precedence)} - H03F 3/3023: {with asymmetrical driving of the end stage} - H03F 3/505: {with field-effect devices} - H03F 2200/144: the feedback circuit of the amplifier stage comprising a passive resistor and passive capacitor - H03F 2200/408: the output amplifying stage of an amplifier comprising three power stages - H03F 2203/30031: A resistor being coupled as feedback circuit in the SEPP amplifier - H03F 2203/30078: A resistor being added in the pull stage of the SEPP amplifier - H03F 2203/30111: A resistor being added in the push stage of the SEPP amplifier - H03F: AMPLIFIERS ## Abstract The invention relates to a feedback network (60) for cascade amplifiers (200), which comprises an active stage (30) to feed signal back to a first internal node (65) at the output of the first amplifier stage (61) of the cascade. The invention further relates to a feedback network (60) which comprises said active feedback stage (30) with said first internal amplifier node (65) connection and a feedback resistor (10) connected from said cascade amplifier output port (out) to its input port (in). ## Claims ### Claim 1 A feedback network (60) for a multistage amplifier, where the amplifier consists of two or more amplifier stages connected in cascade, characterized in that a feedback amplifier stage (30) is connected from circuit output to its first internal node (65) at the output of the first amplifier stage (61) of the 15 cascade. ### Claim 2 (depends on 1) The feedback network according to claim 1, characterized in that said feedback network (60) comprises a feedback resistor (10) connected from cascade amplifier output port to said cascade amplifier input port, and a feedback amplifier stage (30) connected from circuit output to its first internal node (65) at the output of the first amplifier stage of the cascade (61). 20 ### Claim 3 (depends on 1, 2) The feedback network according to claim 1 or 2 characterized in that said feedback amplifier stage (30) is dc-connected to said cascade amplifier output port. ### Claim 4 (depends on 1, 2) The feedback network according to claim 1 or 2 wherein said feedback amplifier stage (30) is characterized in that its output is connected to said first internal node (65) of the cascade amplifier (200) through an impedance network. 25 ### Claim 5 (depends on 1, 2) The feedback network according to claim 1 or 2, characterized in that said feedback network resistor (10) has been realized with N- or PMOS transistor and/or transistors. ### Claim 6 (depends on 1, 2) The feedback network according to claim 1 or 2, characterized in that said feedback network resistor (10) has been realized as a variable valued resistor. ### Claim 7 (depends on 1, 2) The feedback network according to claim 1 or 2, characterized in that said feedback network re-30 sistor (10) has been realized as an impedance circuit comprising of capacitor, resistor, and/or inductor realizations. ### Claim 8 (depends on 2) CMOS transistor realization of the feedback network according to claim 2, which comprises a feedback resistor (10) connected from cascade amplifier output port to said amplifier input port, and a feedback amplifier stage (30) connected from said amplifier output to its first internal node (65) at the output 35 of the first amplifier stage of the cascade (61), characterized in that 17 said feedback amplifier stage (30) comprises a PMOS transistor which mirrors output stage signaling and biasing current as a feedback signal through sensing it with its gate node and delivering its feedback signaling through its drain node directly connected to said first internal node (65); said cascade amplifier comprises three copies of schematically similar biased CMOS amplifier stages (61, 62, 63) which can have different element values each according to desired performance; and 5 wherein said schematically similar biased CMOS amplifier stages have a first NMOS input transistor which is loaded with a PMOS input transistor so as to form current reuse amplifying stages. ### Claim 9 (depends on 2, 8) CMOS transistor realization of the feedback network according to claim 2 or 8 wherein said cascade amplifying stages (61, 62, 63) are dc-connected to mirror first stage biasing and signaling current so that the arrangement is characterized in that said cascade second amplifying stage (62) is dc-connected at 10 its PMOS transistor (34) input gate so that its NMOS input transistor (33) load is biased and linearized with a local feedback resistor (14); said second stage NMOS input transistor (33) gate is driven with input signaling through a dc-blocking capacitor (22); said cascade third amplifying stage (63) is dc-connected at its NMOS transistor (35) input gate so that 15 its PMOS input transistor (36) load is biased and linearized with a local feedback resistor (16); and said third stage PMOS input transistor (36) gate is driven with input signaling through a dc-blocking capacitor (25). ### Claim 10 (depends on 8, 9) Circuits in accordance with claim 8 or 9 characterized in that all or part of the circuit blocks (60, 61, 62, 63) are complementary to said realizations in the sense that N- and PMOS transistor roles and 20 connections have been interchanged. ### Claim 11 A feedback network realization according to any of the preceding claims characterized in that one or both of the integrated dc-blocking capacitors at the cascade amplifier (200) first amplifier stage (61) input have been implemented as external, off-chip, capacitors. ### Claim 12 A feedback network realization according to any of the preceding claims characterized in that the 25 cascade amplifier (200) is preceded by an inductive impedance element. ### Claim 13 A feedback network realization according to any of the preceding claims characterized in that some or all of the the amplifier stages are self-biased. ### Claim 14 A feedback network realization according to any of the preceding claims characterized in that multiple copies of the cascade amplifier (200) have been cascaded to act as an amplifying stage. 30 ### Claim 15 A feedback network realization according to any of the preceding claims characterized in that multiple copies of the cascade amplifier (200) have been connected in parallel to output to multiple output ports. ### Claim 16 A feedback network realization according to any of the preceding claims characterized in that it has been implemented in monolithic form.