# US 2010/0164609 A1 · Circuit for generating reference voltage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164609 A1 - Document ID: US20100164609A1 - Status: Published application - Kind: A1 - Application number: 12/639,834 - Filed: 2009-12-16 - Published: 2010-07-01 - Earliest claimed: 2008-12-30 - Assignees: Dongbu HiTek Co., Ltd. - Inventors: Min-Jong Yoo - Web page: https://patentgrep.com/patent/US20100164609A1 ## CPC - G05F 3/30: Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A reference voltage generating circuit includes a reference voltage generating unit generating a uniform reference voltage in response to a bias voltage, a bias voltage generating unit generating the bias voltage, and a start-up circuit, after activating the bias voltage generating unit by receiving a first supply voltage, canceling a change of the first supply voltage to maintain a separation from the bias voltage generating unit. The circuit adopts a start-up circuit having a voltage distributing unit, thereby preventing a quiescent point of a bias voltage generating unit from entering a zero state and prevents a reference voltage from rising in a power-up state that an analog supply voltage rises according to a change of an external design environment such as a power, a temperature, a process parameter and the like, thereby generating a reference voltage more stably. As a result, current consumption and power consumption are minimized. ## Claims ### Claim 1 A device comprising: a reference voltage generating unit configured to generate a uniform reference voltage in response to a bias voltage; a bias voltage generating unit configured to generate the bias voltage; and a start-up circuit, after activating the bias voltage generating unit by receiving a first supply voltage, configured to cancel a change of the first supply voltage to maintain a separation from the bias voltage generating unit. ### Claim 2 (depends on 1) The device of claim 1, wherein the reference voltage generating unit comprises: a differential amplifier receiving a first node voltage and a second node voltage; a 1st MOS transistor having a gate connected to an output of the differential amplifier, a source drain connected to a second supply voltage and a drain connected to the first node voltage; a 2nd MOS transistor having a gate connected to the output of the differential amplifier, a source connected to the second supply voltage and a drain connected to the second node voltage; a 3rd MOS transistor having a gate connected to the output of the differential amplifier, a source connected to the second supply voltage and a drain connected to the reference voltage; a 1st bipolar transistor having an emitter and collector connected between the first node voltage and a reference potential and a base connected to the reference potential; a 1st resistor connected between the first node voltage and the reference potential; a 2nd resistor having one side connected to the second node voltage; a 2nd bipolar transistor having an emitter connected to the other side of the 2nd resistor, a collector connected to the reference potential and a base connected to the reference potential; a 3rd resistor connected between the second node voltage and the reference potential; and an output resistor connected between the reference voltage and the reference potential. ### Claim 3 (depends on 1) The device of claim 1, wherein the bias voltage generating unit comprises: a 4th MOS transistor having a source and drain connected to the first supply voltage and the bias voltage, respectively; a 5th MOS transistor having a gate connected to the gate of the 4th MOS transistor and a source connected to the first supply voltage; a 6th MOS transistor having a drain and source connected to the bias voltage and the reference potential, respectively; a 4th resistor having one side connected to the reference potential; and a 7th MOS transistor having a gate connected to the gate of the 6th MOS transistor, a drain connected to the drain of the 5th MOS transistor and a source connected to the other side of the 4th resistor. ### Claim 4 A device comprising: a reference voltage generating unit configured to generate a uniform reference voltage in response to a bias voltage; a bias voltage generating unit configured to generate the bias voltage; and a start-up circuit operating in response to an enable signal, the start-up circuit, after activating the bias voltage generating unit by receiving a first supply voltage, configured to cancel a change of the first supply voltage to maintain a separation from the bias voltage generating unit. ### Claim 5 (depends on 4) The device of claim 4, wherein the reference voltage generating unit comprises: a differential amplifier receiving a first node voltage and a second node voltage; a 1st MOS transistor having a gate connected to an output of the differential amplifier, a source drain connected to a second supply voltage and a drain connected to the first node voltage; a 2nd MOS transistor having a gate connected to the output of the differential amplifier, a source connected to the second supply voltage and a drain connected to the second node voltage; a 3rd MOS transistor having a gate connected to the output of the differential amplifier, a source connected to the second supply voltage and a drain connected to the reference voltage; a 1st bipolar transistor having an emitter and collector connected between the first node voltage and a reference potential and a base connected to the reference potential; a 1st resistor connected between the first node voltage and the reference potential; a 2nd resistor having one side connected to the second node voltage; a 2nd bipolar transistor having an emitter connected to the other side of the 2nd resistor, a collector connected to the reference potential and a base connected to the reference potential; a 3rd resistor connected between the second node voltage and the reference potential; and an output resistor connected between the reference voltage and the reference potential. ### Claim 6 (depends on 4) The device of claim 4, the bias voltage generating unit comprises: a 4th MOS transistor having a source and drain connected to the first supply voltage and the bias voltage, respectively; a 5th MOS transistor having a gate connected to the gate of the 4th MOS transistor and a source connected to the first supply voltage; a 6th MOS transistor having a drain and source connected to the bias voltage and the reference potential, respectively; a 4th resistor having one side connected to the reference potential; and a 7th MOS transistor having a gate connected to the gate of the 6th MOS transistor, a drain connected to the drain of the 5th MOS transistor and a source connected to the other side of the 4th resistor. ### Claim 7 (depends on 6) The device of claim 6, wherein the start-up circuit comprises: an 8th MOS transistor having a source and drain connected to the first supply voltage and the bias voltage, respectively; a 9th MOS transistor having a gate connected to the gate of the 8th MOS transistor and a source connected to the first supply voltage; a 10th MOS transistor having a drain connected to a drain of the 9th MOS transistor and a source connected to the reference potential; an 11th MOS transistor having a source connected to the first supply voltage and a gate and drain connected to each other; a 12th MOS transistor having a gate connected to the first supply voltage and a source connected to the reference potential; and a voltage distributing unit connected between the drain of the 11th MOS transistor and a drain of the 12th MOS transistor, the voltage distributing unit supplying a gate of the 10th MOS transistor with a uniform control voltage for canceling a change of the first supply voltage. ### Claim 8 (depends on 7) The device of claim 7, wherein the voltage distributing unit comprises: a 13th MOS transistor having a source connected to the drain of the 11th MOS transistor and a drain connected to the control voltage; and a 14th MOS transistor having a drain connected to the control voltage, a source connected to the drain of the 12th MOS transistor and a gate connected to a gate of the 13th MOS transistor. ### Claim 9 (depends on 7) The device of claim 7, wherein the voltage distributing unit comprises: at least a fifth resistor and a sixth resistor connected in serial between the drain of the 11th MOS transistor and the drain of the 12th MOS transistor, wherein the control voltage is generated from a connected portion of the fifth resistors and sixth resistor. ### Claim 10 (depends on 7) The device of claim 7, the wherein voltage distributing unit comprises: at least two capacitors connected in serial between the drain of the 11th MOS transistor and the drain of the 12th MOS transistor, wherein the control voltage is generated from a connected portion of the capacitors. ### Claim 11 (depends on 7) The device of claim 7, wherein the voltage distributing unit comprises: a 3rd bipolar transistor having a collector connected to the drain of the 11th MOS transistor and an emitter connected to the control voltage; and a 4th bipolar transistor having a collector connected to the control voltage, an emitter connected to the drain of the 12th MOS transistor and a base connected to the base and emitter of the 3rd bipolar transistor. ### Claim 12 (depends on 7) The device of claim 7, the voltage distributing unit comprising: a 1st diode having an anode connected to the drain of the 11th MOS transistor and a cathode connected to the control voltage; and a 2nd diode having an anode connected to the control voltage and a cathode connected to the drain of the 12th MOS transistor. ### Claim 13 (depends on 8) The device of claim 8, wherein the start-up circuit comprises: a 15th MOS transistor having a source and drain respectively connected to the source and drain of the 8th MOS transistor and a gate connected to the enable signal; a 17th MOS transistor having a drain connected to the drain of the 11th MOS transistor, a source connected to the voltage distributing unit and a gate connected to the enable signal; and a 16th MOS transistor having a drain connected to the source of the 10th MOS transistor, a source connected to the reference potential and a gate connected to the enable signal. ### Claim 14 (depends on 4) The device of claim 4, wherein the enable signal is generated when the uniform reference voltage is externally supplied instead of being generated from the reference voltage generating unit and wherein the enable signal is provided to the start-up circuit. ### Claim 15 (depends on 4) The device of claim 4, wherein the enable signal is generated in a power-down mode. ### Claim 16 (depends on 4) The device of claim 4, wherein the enable signal is generated in a standby mode. ### Claim 17 A method comprising: generating, from a reference voltage generating unit, a uniform reference voltage in response to a bias voltage; generating, from a bias voltage generating unit, the bias voltage; and in response to an enable signal, activating the bias voltage generating unit by receiving a first supply voltage, and canceling a change of the first supply voltage to maintain a separation from the bias voltage generating unit. ### Claim 18 (depends on 17) The method of claim 17, wherein the enable signal is generated in a power-down mode. ### Claim 19 (depends on 17) The method of claim 17, wherein the enable signal is generated in a standby mode. ### Claim 20 (depends on 17) The method of claim 17, wherein the enable signal is generated when the uniform reference voltage is externally supplied instead of being generated from the reference voltage generating unit.