# US 2010/0164607 A1 · Semiconductor device that can adjust substrate voltage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164607 A1 - Document ID: US20100164607A1 - Status: Published application - Kind: A1 - Application number: 12/647,259 - Filed: 2009-12-24 - Published: 2010-07-01 - Earliest claimed: 2008-12-25 - Assignees: Elpida Memory, Inc. - Inventors: Shinichi Miyatake; Seiji Narui; Hitoshi Tanaka - Web page: https://patentgrep.com/patent/US20100164607A1 ## CPC - G05F 3/205: {Substrate bias-voltage generators (for static stores G11C5/146)} - G05F 1/46: wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value. ## Claims ### Claim 1 A semiconductor device, comprising: a first MOS transistor formed in a semiconductor substrate; at least one replica transistor of the first MOS transistor; a monitoring circuit that monitors a gate/source voltage of the replica transistor needed when the replica transistor flows a current having a given designed value; a voltage generating circuit that generates a substrate voltage of the first MOS transistor based on an output from the monitoring circuit; and a limiting circuit that defines an operation of the voltage generating circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the limiting circuit activates the voltage generating circuit regardless of the monitoring result of the monitoring circuit when a level of the substrate voltage is higher than a first level. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, wherein the limiting circuit inactivates the voltage generating circuit regardless of the monitoring result of the monitoring circuit when a level of the substrate voltage is lower than a second level. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein the monitoring circuit includes: a constant current circuit that supplies the current having the given designed value to the replica transistor; and an operational amplifier that constantly maintains the source/drain voltage of the replica transistor. ### Claim 5 (depends on 4) The semiconductor device as claimed in claim 4, wherein the given designed value is a designed value of a drain current of the first MOS transistor when the first MOS transistor is turned off. ### Claim 6 (depends on 4) The semiconductor device as claimed in claim 4, wherein the given designed value is a designed value of a drain current of the first MOS transistor when the first MOS transistor is turned on. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, wherein a plurality of replica transistors are provided, the monitoring circuit monitors an average of gate/source voltages needed when each of the plurality of replica transistors flows the current having the given designed value. ### Claim 8 (depends on 1) The semiconductor device as claimed in claim 1, further comprising a second MOS transistor formed in the semiconductor substrate and supplied with a voltage generated by the voltage generating circuit to a substrate thereof, wherein the first and second MOS transistors are included in different circuits from each other that are formed in different circuit blocks and have different functions. ### Claim 9 (depends on 8) The semiconductor device as claimed in claim 8, wherein the first and second MOS transistors are formed in a same well formed in the semiconductor substrate, and the voltage generated by the voltage generating circuit is supplied to the well. ### Claim 10 (depends on 8) The semiconductor device as claimed in claim 8, wherein the first MOS transistor is a transistor included in a sense amplifier, the second MOS transistor is a transistor included in a memory cell, and the sense amplifier and the memory cell are connected through a bit line. ### Claim 11 A semiconductor device comprising: a first region supplied with a substrate bias voltage; a first transistor formed in the first region, and including a first gate electrode and first source and drain regions; a monitor circuit monitoring a level of the substrate bias voltage; a voltage generating circuit generating the substrate bias voltage; and a control circuit controlling the voltage generating circuit in response to an output of the monitor circuit and a gate voltage of the first gate electrode of the first transistor. ### Claim 12 (depends on 11) The semiconductor device as claimed in claim 11, further comprising: a current source coupled to the first drain region; and an additional control circuit supplied with a reference voltage, wherein the additional control circuit controls the gate voltage of the first gate electrode so that a voltage between the first source and drain regions is equalized to the reference voltage. ### Claim 13 (depends on 12) The semiconductor device as claimed in claim 12, further comprising: a second region supplied with the substrate bias voltage; and a second transistor formed in the second region, wherein the second transistor includes a second gate electrode and second source and drain regions, and a voltage between the second source and drain regions rendered to be non-conductive is substantially equal to the reference voltage. ### Claim 14 (depends on 13) The semiconductor device as claimed in claim 13, further comprising a third transistor formed in the second region, wherein the second transistor includes a part of sense amplifier, and the third transistor includes a memory cell transistor.