# US 2010/0164597 A1 · Bootstrap Transistor Circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0164597 A1 - Document ID: US20100164597A1 - Status: Published application - Kind: A1 - Application number: 12/628,945 - Filed: 2009-12-01 - Published: 2010-07-01 - Earliest claimed: 2008-12-31 - Assignees: Linear Technology Corporation - Inventors: Jesper Steensgaard-Madsen - Web page: https://patentgrep.com/patent/US20100164597A1 ## CPC - H03K 17/102: {in field-effect transistor switches} - H03K 17/063: {in field-effect transistor switches} - H03K 17/162: {without feedback from the output circuit to the control circuit} - H03K 2217/0054: Gating switches, e.g. pass gates - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state. ## Claims ### Claim 1 A circuit comprising: a switch comprising a first semiconductor device having a first control terminal, a second terminal, and a third terminal; a driver circuit; and a bootstrap circuit coupled to the driver circuit, the bootstrap circuit comprising: a capacitor selectively connected via the driver circuit to a charging voltage source for charging the capacitor to a bootstrap voltage during an off state of the switch; a latching circuit coupled to the capacitor and the first semiconductor device, wherein, during an on state of the switch, the latching circuit is in a latched conductive state connecting the capacitor across the first control terminal and the second terminal of the first semiconductor device. ### Claim 2 (depends on 1) The circuit of claim 1 wherein the switch comprises the first semiconductor device connected to a second semiconductor device, the first semiconductor device being a first MOSFET and the second semiconductor device being a second MOSFET, a gate terminal of the first MOSFET being connected to a gate terminal of the second MOSFET, a source terminal of the first MOSFET being connected to a source terminal of the second MOSFET, a drain terminal of the first MOSFET being an input terminal of the switch, and a drain terminal of the second MOSFET being an output terminal of the switch. ### Claim 3 (depends on 2) The circuit of claim 2 wherein the first semiconductor device is an asymmetrical MOSFET having a gate-drain breakdown voltage higher than a gate-source breakdown voltage. ### Claim 4 (depends on 3) The circuit of claim 3 wherein the latching circuit comprises a symmetrical MOSFET transistor. ### Claim 5 (depends on 1) The circuit of claim 1 wherein the first semiconductor device is an asymmetrical semiconductor device having a first reliability voltage limit with respect to voltages applied between the first control terminal and the second terminal and a second reliability voltage limit with respect to voltages applied between the first control terminal and the third terminal; an absolute value of the second reliability voltage limit exceeding an absolute value of the first reliability voltage limit. ### Claim 6 (depends on 5) The circuit of claim 5 wherein a voltage signal is applied to the third terminal of the first semiconductor device, the applied voltage signal having a peak-to-peak excursion exceeding the first reliability voltage limit. ### Claim 7 (depends on 1) The circuit of claim 1 wherein the driver circuit comprises an asymmetrical MOSFET transistor having a gate-drain breakdown voltage higher than a gate-source breakdown voltage. ### Claim 8 (depends on 1) The circuit of claim 1 wherein the driver circuit contains transistors connected to the capacitor and the latching circuit, wherein the transistors are configured to disconnect the capacitor from the charging voltage source during the on state of the switch and establish a predetermined non-zero voltage across the latching circuit during the off state of the switch. ### Claim 9 (depends on 1) The circuit of claim 1 wherein the driver circuit provides a plurality of controllable connections to the capacitor, the latching circuit, and the switch, wherein each of the plurality of controllable connections is substantially non-conductive during the on state of the switch. ### Claim 10 (depends on 1) The circuit of claim 1 wherein the latching circuit comprises a bootstrapped semiconductor device. ### Claim 11 (depends on 1) The circuit of claim 1 wherein the latching circuit comprises a semiconductor device having a gate terminal connected to the second terminal of the first semiconductor device. ### Claim 12 (depends on 1) The circuit of claim 1 wherein a conductivity of the latching circuit in the on state of the switch is substantially independent of a voltage potential on the second terminal of the first semiconductor device. ### Claim 13 (depends on 1) The circuit of claim 1 wherein the latching circuit comprises a first PMOS transistor and a first NMOS transistor, a gate terminal of the first PMOS transistor being connected to a drain terminal of the first NMOS transistor, a gate terminal of the first NMOS transistor being connected to a drain terminal of the first PMOS transistor, and wherein the capacitor is coupled between a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor. ### Claim 14 (depends on 13) The circuit of claim 13 wherein the latching circuit further comprises a second PMOS transistor, a gate terminal of the second PMOS transistor being connected to the gate terminal of the first NMOS transistor, a source terminal of the second PMOS transistor being connected to the source terminal of the first PMOS transistor, and a drain terminal of the second PMOS transistor being connected to the drain terminal of the first NMOS transistor. ### Claim 15 (depends on 13) The circuit of claim 13 wherein the latching circuit further comprises a second NMOS transistor, a gate terminal of the second NMOS transistor being connected to the gate terminal of the first PMOS transistor, a source terminal of the second NMOS transistor being connected to the source terminal of the first NMOS transistor, and a drain terminal of the second NMOS transistor being connected to the drain terminal of the first PMOS transistor. ### Claim 16 (depends on 13) The circuit of claim 13 wherein the first semiconductor device comprises a second NMOS transistor, wherein the first control terminal is a gate terminal of the second NMOS transistor, the second terminal of the first semiconductor device is a source terminal of the second NMOS transistor, and the third terminal of the first semiconductor device is a drain terminal of the second NMOS transistor, and wherein the source terminal of the first NMOS transistor is connected to the source terminal of the second NMOS transistor. ### Claim 17 (depends on 16) The circuit of claim 16 wherein the switch further comprises a third NMOS transistor connected to the second NMOS transistor, the gate terminal of the second NMOS transistor being connected to a gate terminal of the third NMOS transistor, the source terminal of the second NMOS transistor being connected to a source terminal of the third NMOS transistor, the drain terminal of the second NMOS transistor being an input terminal of the switch, and a drain terminal of the third NMOS transistor being an output terminal of the switch. ### Claim 18 (depends on 1) The circuit of claim 1 wherein the driver circuit comprises: a first driver semiconductor device configured to apply a first predetermined voltage level to a first terminal of the capacitor in the off state of the switch; a second driver semiconductor device configured to apply a second predetermined voltage level to the second terminal of the first semiconductor device in the off state of the switch; and a third driver semiconductor device configured to apply a third predetermined voltage level to the first control terminal of the first semiconductor device in the off state of the switch. ### Claim 19 (depends on 18) The circuit of claim 18 wherein the first driver semiconductor device, the second driver semiconductor device, and the third driver semiconductor device are substantially non-conductive during the on state of the switch. ### Claim 20 (depends on 18) The circuit of claim 18 wherein a gate terminal of the first driver semiconductor device is connected to the first control terminal of the first semiconductor device. ### Claim 21 (depends on 20) The circuit of claim 20 wherein a gate terminal of the third driver semiconductor device is biased at the first predetermined voltage level. ### Claim 22 (depends on 1) The circuit of claim 1 further comprising a subcircuit to inject a charge pulse to cause the latching circuit to latch in the latched conductive state. ### Claim 23 (depends on 1) The circuit of claim 1 wherein the first semiconductor device is an asymmetrical semiconductor device comprising a gate oxide having a thickness that is substantially the same as a thickness of a gate oxide used to implement symmetrical semiconductor devices on a shared substrate. ### Claim 24 A method of controlling a switch, the switch comprising a first semiconductor device having a first control terminal, a second terminal, and a third terminal, the method comprising the steps of: in an off state of the switch, charging a capacitor having a first terminal coupled to a charging voltage source and a second terminal, the first terminal of the capacitor being coupled to the charging voltage source by a second semiconductor device; in the off state of the switch, applying a non-zero voltage across a latching circuit, the latching circuit being coupled between the first terminal of the capacitor and the first control terminal of the first semiconductor; and toggling the switch to be in an on state by controlling the second semiconductor device to disconnect the first terminal of the capacitor from the charging voltage source, and causing the latching circuit to latch to couple the first terminal of the capacitor to the first control terminal of the first semiconductor device to provide a bootstrap voltage between the first control terminal and the second terminal of the first semiconductor device. ### Claim 25 (depends on 24) The method of claim 24 wherein the non-zero voltage applied across the latching circuit in the off state of the switch is substantially the highest static voltage difference that occurs across any gate oxide that is a part of a semiconductor device used to implement the latching circuit. ### Claim 26 (depends on 24) The method of claim 24 further comprising the step of, during the on state of the switch, maintaining tracking voltage potentials on each side of a gate oxide embodied in the latching circuit, each of the tracking voltage potentials having a substantially constant voltage difference with respect to the second terminal of the first semiconductor device. ### Claim 27 (depends on 24) The method of claim 24 wherein the latching circuit comprises a bootstrapped switch. ### Claim 28 (depends on 24) The method of claim 24 wherein the latching circuit comprises a circuit element, which in the on state provides a conductive path between the first terminal of the capacitor and the first control terminal of the first semiconductor; an impedance of the conductive path being substantially independent of a voltage potential on the second terminal of the first semiconductor. ### Claim 29 (depends on 24) The method of claim 24 wherein the switch comprises the first semiconductor device connected to a third semiconductor device, the first semiconductor device and the third semiconductor device being MOSFETs, a gate terminal of the first MOSFET semiconductor device being connected to a gate terminal of the third MOSFET semiconductor device, a source terminal of the first MOSFET semiconductor device being connected to a source terminal of the third MOSFET semiconductor device, a drain terminal of the first MOSFET semiconductor device being an input terminal of the switch, and a drain terminal of the third MOSFET semiconductor device being an output terminal of the switch. ### Claim 30 (depends on 29) The method of claim 29 wherein the first MOSFET semiconductor device is an asymmetrical MOSFET semiconductor device having a gate-drain breakdown voltage higher than a gate-source breakdown voltage. ### Claim 31 (depends on 24) The method of claim 24 wherein the steps of charging the capacitor and toggling the switch to be in its on state comprises the step of supplying signals to the latching circuit by a driver circuit comprising semiconductor devices, the method further comprising the steps of: controlling the second semiconductor device connected between the first terminal of the capacitor and the charging voltage source for charging the capacitor during the off state of the switch; controlling a second driver semiconductor device connected to the latching circuit for applying the non-zero voltage across the latching circuit during the off state of the switch; and controlling a third driver semiconductor device for applying a substantially fixed potential to the first control terminal of the first semiconductor device during the off state of the switch. ### Claim 32 (depends on 24) The method of claim 24 wherein the latching circuit comprises a first PMOS transistor and a first NMOS transistor, a gate terminal of the first PMOS transistor being coupled to a drain terminal of the first NMOS transistor, a gate terminal of the first NMOS transistor being coupled to a drain terminal of the first PMOS transistor; the capacitor being connected between a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor. ### Claim 33 (depends on 24) The method of claim 24 wherein the second semiconductor device provides a connection via a diode junction between the charging voltage source and the first terminal of the capacitor. ### Claim 34 A method for controlling a switch, the switch having a control terminal, a middle terminal, an input switch terminal, and an output switch terminal; the method comprising the steps of: providing a capacitor having a first capacitor terminal and a second capacitor terminal; providing a connecting circuit having a first connecting terminal and a second connecting terminal; in an off state of the switch, applying a first predetermined voltage between the first connecting terminal and the second connecting terminal, and applying a second predetermined voltage between the first capacitor terminal and the second capacitor terminal; and in an on state of the switch, equalizing the potentials of the first connecting terminal and the second connecting terminal, thereby effectively connecting the capacitor between the middle terminal and the control terminal of the switch, whereby, in the on state of the switch, a conductive path is established between the input switch terminal and the output switch terminal; the conductive path traversing the middle terminal. ### Claim 35 (depends on 34) The method of claim 34 wherein the switch comprises an asymmetrical semiconductor device. ### Claim 36 (depends on 34) The method of claim 34 wherein the switch comprises a first semiconductor device having a first-control terminal connected to the control terminal, a first-second terminal connected to the middle terminal, and a first-third terminal connected to the input switch terminal; the switch further comprising a second semiconductor device having a second-control terminal connected to the control terminal, a second-second terminal connected to the middle terminal, and a second-third terminal connected to the output switch terminal. ### Claim 37 (depends on 36) The method of claim 36 wherein the first semiconductor device can tolerate greater voltages to be applied between its first-third terminal and its first-control terminal, compared to voltages that may be applied between its first-control terminal and its first-second terminal without risking an accelerated degradation of an electrical property of the first semiconductor device. ### Claim 38 (depends on 34) The method of claim 34 wherein the connecting circuit comprises a bootstrapped switch. ### Claim 39 (depends on 34) The method of claim 34 wherein the connecting circuit comprises a first PMOS transistor and a first NMOS transistor, a gate terminal of the first PMOS transistor being coupled to a drain terminal of the first NMOS transistor, a gate terminal of the first NMOS transistor being coupled to a drain terminal of the first PMOS transistor; the capacitor being connected between a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor. ### Claim 40 (depends on 34) The method of claim 34 wherein the connecting circuit comprises a first PMOS transistor and a resistor, a gate terminal of the first PMOS transistor being coupled to a first terminal of the resistor, a second terminal of the resistor being connected to the middle terminal of the switch, a source terminal of the first PMOS transistor being connected to the second connecting terminal, and a drain terminal of the first PMOS transistor being connected to the first connecting terminal. ### Claim 41 (depends on 34) The method of claim 34 wherein the connecting circuit comprises a resistor coupled between the first connecting terminal and the second connecting terminal. ### Claim 42 (depends on 34) The method of claim 34 wherein the step of applying the first predetermined voltage between the first connecting terminal and second connecting terminal comprises the step of providing an interface circuit comprising a first PMOS transistor and a first NMOS transistor, a gate terminal of the first PMOS transistor being connected to a drain terminal of the first NMOS transistor, a gate terminal of the first NMOS transistor being connected to a drain terminal of the first PMOS transistor. ### Claim 43 (depends on 42) The method of claim 42 wherein the drain terminal of the first NMOS transistor is connected to the first connecting terminal, a source terminal of the first PMOS transistor is connected to the second connecting terminal, and the step of equalizing the potentials of the first connecting terminal and second connecting terminal comprises the step of applying to a source terminal of the first NMOS transistor a control signal having a on-state voltage level that is higher than an off-state voltage level that the control signal has in the off state of the switch. ### Claim 44 (depends on 43) The method of claim 43 wherein the on-state and off-state voltage levels of the control signal correspond to a logic-high voltage level and a logic-low voltage level of a CMOS logic circuit.